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參數(shù)資料
| 型號： | TSXPC603RCA10LC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 233 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CAVITY UP, CERQUAD-240 |
| 文件頁數(shù)： | 39/40頁 |
| 文件大?。?/td> | 670K |
| 代理商： | TSXPC603RCA10LC |
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TSPC603r
in CERQUAD and MQUAD Packages
3. SIGNAL DESCRIPTION
Figure 3, AUCUN LIEN and AUCUN LIEN describe the signals on the TSPC603r and indicate signal functions. The test signals,
TRST, TMS, TCK, TDI and TDO, comply with subset P-1149.1 of the IEEE testability bus standard.
The 3 signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use only and must be pulled up to VDD for
normal machine operations.
BR
BG
ABB
TS
TT[0-4]
AP[0-3]
APE
TBST
TSIZ[0-2]
GBL
CI
WT
CSE[0-1]
TC[0-1]
AACK
ARTRY
SYSCLK
CLK_OUT
PLL_CFG[0-3]
DBG
DBWO
DBB
DPE
DP[0-7]
DH[0-31], DL[0-31]
A[0-31]
DBDIS
TA
DRTRY
TEA
INT, SMI
MCP
HRESET, SRESET
CKSTP_IN, CKSTP_OUT
RSRV
QREQ, QACK
TBEN
TLBISYNC
TRST, TCK, TMS, TDI, TD0
5
LSSD_MODE,
L1_TSTCLK, L2_TSTCLK
3
1
VDD
OVDD
GND
AVDD
ADDRESS
ARBITRATION
ADDRESS
START
ADDRESS
BUS
TRANSFER
ATTRIBUTE
ADDRESS
TERMINATION
CLOCKS
DATA
ATTRIBUTION
DATA
TRANSFER
DATA
TERMINATION
INTERRUPTS
CHECKSTOPS
RESET
PROCESSOR
STATUS
JTAG/COP
INTERFACE
LSSD TEST
CONTROL
POWER SUPPLY
64
8
1
2
1
2
1
2
1
20
19
40
1
32
4
1
5
3
1
2
4
1
2
1
603r
VOLTDETGND
1
POWER SUPPLY
INDICATOR
Figure 3 : Functional signal groups
Table 3.Address and data bus signal index
Signal name
Mnemonic
Signal function
Signal
type
Address bus
A[0-31]
if output, physical address of data to be transferred.
if input, represents the physical address of a snoop operation.
I/O
Data bus
DH[0-31]
Represents the state of data, during a data write operation if output, or
during a data read operation if input.
I/O
Data bus
DL[0-31]
Represents the state of data, during a data write operation if output, or
during a data read operation if input.
I/O
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