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參數(shù)資料
| 型號： | TSXPC603RCA10LC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 233 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CAVITY UP, CERQUAD-240 |
| 文件頁數(shù)： | 8/40頁 |
| 文件大小： | 670K |
| 代理商： | TSXPC603RCA10LC |
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16/40
TSPC603r
in CERQUAD and MQUAD Packages
3.7. Marking
The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and
permanently marked with the following information as minimum :
- Thomson logo,
- Manufacturer’s part number,
- Class B identification if applicable,
- Date-code of inspection lot,
- ESD identifier if available,
- Country of manufacturing.
4. ELECTRICAL CHARACTERISTICS
4.1. General requirements
All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given
below :
- Table 8 : Static electrical characteristics for the electrical variants.
- Tables 9, 10 and 11 : Dynamic electrical characteristics for the 603r.
These specifications are for 166 MHz to 200 MHz processor core frequencies. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG0 to PLL_CFG3 signals. All timings are specified respective to the rise
edge of SYSCLK.
4.2. Static characteristics
Table 8.Electrical characteristics
Vdd = AVdd = 2.5 V
± 5 % ; OVdd = 3.3 ± 5 % V dc, GND = 0 V dc, –55°C ≤ TC ≤ 125°C
Characteristics
Symbol
Min
Max
Unit
Input high voltage (all inputs except SYSCLK)
VIH
2.0
5.5
V
Input low voltage (all inputs except SYSCLK)
VIL
GND
0.8
V
SYSCLK input high voltage
CVIH
2.4
5.5
V
SYSCLK input low voltage
CVIL
GND
0.4
V
Input leakage current
Vin = 3.465 V(1, 3)
Iin
-
30
mA
Vin = 5.5 V(1, 3)
Iin
-
300
mA
Hi-Z (off-state)
Vin = 3.465 V(1, 3)
leakage current
ITSI
-
30
mA
Vin = 5.5 V(1, 3)
ITSI
-
300
mA
Output high voltage
IOH = –7 mA
VOH
2.4
-
V
Output low voltage
IOL = +7 mA
VOL
-
0.4
V
Capacitance, Vin = 0 V, f = 1 MHz(2)
(excludes TS, ABB, DBB, and ARTRY)
Cin
-
10.0
pF
Capacitance, Vin = 0 V, f = 1 MHz(2)
(for TS, ABB, DBB, and ARTRY)
Cin
-
15.0
pF
Notes:
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals).
2. Capacitance is periodically sampled rather than 100 % tested.
3.Leakage currents are measured for nominal OVdd and Vdd or both OVdd and Vdd. Same variation (for example, both Vdd and OVdd vary by
either +5 % or –5 %).
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