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| 型號： | TSXPC603RCA10LC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 233 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CAVITY UP, CERQUAD-240 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 670K |
| 代理商： | TSXPC603RCA10LC |
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TSPC603r
in CERQUAD and MQUAD Packages
29/40
The PowerPC architecture support four types of exceptions :
D Synchronous, precise - These are causes by instructions. All instruction-caused exceptions are handled precisely ; that is, the
machine state at the time the exception occurs is known and can be completely restored. This means that (excluding the trap and
system call exceptions) the address of the faulting instruction is provided to the exception handler and that neither the faulting
instruction nor subsequent instructions in the code stream will complete execution before the exception is taken. Once the excep-
tion is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exception
handler). When an exception is taken due to an trap or system call instruction, execution resumes at an address provided by the
handler.
D Synchronous, imprecise - The PowerPC architecture defines two imprecise floating-point exception modes, recoverable and
nonrecoverable. Even though the 603r provides a means to enable he imprecise modes, it implements these modes identically
to the precise mode (-hat is, all enabled floating-point enabled exceptions are always precise on the 603r).
D Asynchronous, maskable - The external, SMI, and decrementer interrupts are maskable asynchronous exceptions. When these
exceptions occur, their handling is postponed until the next instruction, and any exceptions associated with that instruction, com-
pletes execution. If there are no instructions in the execution units, the exception is taken immediately upon determination of the
correct restart address (for loading SRR0).
D Asynchronous, non maskable - There are two non maskable asynchronous exceptions: system reset and the machine check
exception. These exceptions may not be recoverable, or may provide a limited degree of recoverability. All exceptions report
recoverability through the SMR[RI] bit.
5.4.2. PowerPC 603r microprocessor exception model
A specified by the PowerPC architecture, all 603r exceptions can be described as either precise or imprecise and either synchronous
or asynchronous. Asynchronous exceptions (some or which are maskable) are caused by events external to the processor’s execu-
tion ; synchronous exceptions, which are all handled precisely by the 603r, are caused by instructions. The 603r exception classes
are shown in Table 13.
Synchronous/Asynchronous
precise/Imprecise
Exception type
Asynchronous, non maskable
Imprecise
Machine check
System reset
Asynchronous, maskable
Precise
External interrupt
Decrementer
System management interrupt
Synchronous
Precise
Instruction-caused exceptions
Table 13.PowerPC 603r microprocessor exception classifications
Although exceptions have other characteristics as well, such as whether they are maskable or non maskable, the distinctions shown
in Table 13 define categories of exceptions that the 603r handles uniquely. Note that Table 13 includes no synchronous imprecise
instructions. While the PowerPC architecture supports imprecise handling of floating-point exceptions, the 603r implements these
exception modes as precise exceptions.
The 603r’s exceptions, and conditions that cause them, are listed in Table 14. Exceptions that are specific to the 603r are indicated.
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