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參數(shù)資料
| 型號： | TSXPC603RCA10LC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 233 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CAVITY UP, CERQUAD-240 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 670K |
| 代理商： | TSXPC603RCA10LC |
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TSPC603r
in CERQUAD and MQUAD Packages
D Most functional units disabled.
D Bus snooping and time base/decrementer still enabled.
D Dose mode sequence :
- Set doze bit (HID0[8) = 1).
- 603r enters doze mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SMI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
D Transition to full-power state takes no more than a few processor cycles.
D PLL running and locked to SYSCLK.
4.
Nap Mode
The nap mode disables the 603r but still maintains the phase locked loop (PLL) and the time base/decrementer. The time base can be
used to restore the 603r to full-on state after a programmed amount of time. Because bus snooping is disabled for nap and sleep
mode, a hardware handshake using the quiesce request (QREQ) and quiesce acknowledge (QACK) signals are requires to maintain
data coherency. The 603r will assert the QREQ signal to indicate that it is ready to disable bus snooping. When the system has
ensured that snooping is no longer necessary, it will assert QACK and the 603r will enter the sleep or nap mode.
D Time base/decrementer still enabled.
D Most functional units disabled (including bus snooping).
D All nonessential input receivers disables.
D Nap mode sequence :
- Set nap bit (HID0[9] = 1).
- 603r asserts quiesce request (QREQ) signal.
- System asserts quiesce acknowledge (QACK) signal.
- 603r enters sleep mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SPI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
D Transition to full-power takes no more than a few processor cycles.
D PLL running and locked to SYSCLK.
5.
Sleep Mode
Sleep mode consumes the least amount of power of the four modes since all functional units are disabled. To conserve the maximum
amount of power, the PLL may be disabled and the SYSCLK may be removed. Due to the fully static design of the 603r, internal proc-
essor state is preserved when no internal clock is present. Because the time base and decrementer are disabled while the 603r is in
sleep mode, the 603r’s time base contents will have to be updated from an external time base following sleep mode if accurate time-of-
day maintenance is required. Before the 603r enters the sleep mode, the 603r will assert the QREQ signal to indicate that it is ready to
disable bus snooping. When the system has ensured that snooping is no longer necessary, it will assert QACK and the 603r will enter
the sleep mode.
D All functional units disabled (including bus snooping and time base).
D All nonessential input receivers disabled :
- Internal clock regenerators disabled.
- PLL still running (see below).
D Sleep mode sequence :
- Set sleep bit (HID0[10] = 1).
- 603r asserts quiesce request (QREQ).
- System asserts quiesce acknowledge (QACK).
- 603r enters sleep mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SMI, or MCP interrupts.
- Assert hard reset or soft reset.
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