參數(shù)資料
型號: TSB42AA9I
廠商: Texas Instruments, Inc.
英文描述: STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
中文描述: STORAGELYNX 1394鏈路層的ATA控制器/ ATAPI儲存產(chǎn)品
文件頁數(shù): 70/183頁
文件大?。?/td> 798K
代理商: TSB42AA9I
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55
Table 55. Bit Description for Packet Control Token
BIT NAME
DESCRIPTION
Size
Size of the packet in quadlets
S
This bit is set when the token is attached to a self-ID packet.
P
This bit is set when the token is attached to a PHY packet.
rsv
Reserved
ACK
ACK code from the link receiver (5 bits). ACK code meanings are explained in Table 510.
pad
Number of bytes padded (e.g. data_length = 9
pad = 3)
spd
Speed code of the received packet
The default configuration for ceLynx is receive asynchronous data through buffer 5. The self-ID packets and
PHY configuration packets are received through buffer 6. These configurations can be changed in the
STREAMTYPE bits in the DB(N)CFG0 registers.
The asynchronous receive control bits are located in register RXDP(N)CFG1. These bits are active only
when the associated buffer is configured and enabled for asynchronous receive. Table 56 includes
information on asynchronous receive control. There are four general categories for asynchronous receive
control: nonbroadcast asynchronous, broadcast asynchronous, self-IDs, and PHY packets. Any
combination of control bits can be used for a selected buffer,
except
broadcast and nonbroadcast packets
cannot be received in the same buffer with a fixed configuration.
The receive asynchronous packet is steered to the lowest numbered buffer whose requirements are
satisfied.
Table 56. Asynchronous Receive Control
ASYNCHRONOUS PACKET RECEIVED
If set, then
only
broadcast packets are received by the selected buffer. This includes packets with
3FF destination ID only.
If set, then PHY packets are received by the selected buffer. This control bit can be used in
conjunction with any of the other control bits.
If set, then self-ID packets are received to the selected buffer. This control bit can be used in
conjunction with any of the other control bits.
If set, then all nonbroadcast asynchronous packets addressed to this node are received by the
selected buffer regardless of the 48-bit serial bus address contained in the asynchronous packet
header. This does not include PHY packets, self-ID packets, or broadcast packets.
CONTROL BIT
BROADCAST
RCVPHYPKT
RCVSELFID
RCVALLADDR
INITMEMLO
Destination address: bus, node, 00000, 0000000
If set, then all asynchronous packets addressed to lower half of initial space of IEEE 1394-1995 are
received by the selected buffer. This only includes packets with destination address between (bus,
node, 00000,0000000
bus, node, 7FFFF, FFFFFFF). This does not include PHY packets, self-ID
packets, or broadcast packets.
Destination address: bus, node, 80000, 0000000
If set, then all asynchronous packets addressed to upper half of initial space of IEEE 1394-1995 are
received to the selected buffer. This only includes packets with destination address between (bus,
node, 80000, 0000000
bus, node, FFFFD, FFFFFFF). This does not include PHY packets, self-ID
packets, or broadcast packets.
Destination address: bus, node, FFFFE, 0000000
If set, then all asynchronous packets addressed to private memory space specified by IEEE
1394-1995 are received by the selected buffer. This only includes packets with destination address
between (bus, node, FFFFE, 0000000
bus, node, FFFFE, FFFFFFF).
This does not include PHY
packets, self-ID packets, or broadcast packets.
bus, node, 7FFFF, FFFFFFF
INITMEMHI
bus, node, FFFFD, FFFFFFF
PRIVATE
bus, node, FFFFE, FFFFFFF
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