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| 型號(hào)： | TSB42AA9I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| 中文描述： | STORAGELYNX 1394鏈路層的ATA控制器/ ATAPI儲(chǔ)存產(chǎn)品 |
| 文件頁(yè)數(shù)： | 178/183頁(yè) |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AA9I |
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81
8 Hardware Errata
8.1
MCIF_ACK Pin Functionality
Section:
3.1.4
When operating the ceLynx host interface in multistrobe mode, the MCIF_ACK is not
asserted at the correct time for read or write mode.
Workaround: Avoid using multistrobe mode if possible. This can be accomplished by using
an AND-gate to generate active-low MCIF_STRB from read-strobe and write-strobe
(assuming active-low signalling). The read-strobe or the write-strobe (again depending on
signalling) can then be connected directly to the MCIF_RW pin to indicate direction. If
multistrobe mode is required without external logic, use an auto-acknowledge/self-
acknowledge mode on the host processor that automatically terminates the read or write
access after a period greater than 114 ns.
8.2
JTAG
Section:
2.5.1.5
8.3
JTAG works in bypass mode only. For details, refer to Notes in section 2.5.1.5.
Link Layer Controller(LLC)
Section:
6.3
Incorrect Cycle Lost Interrupt . When a series of conditions occur in an unlikely combination,
the link layer may falsely declare a cycle lost condition and generate a false interrupt. If the
external HW (external to the link), or SW utilizes this interrupt this may cause problem opera-
tion. If the node’s HW or SW does not utilize this interrupt, there is no problem.
Workaround : Do not respond to a cycle lost interrupt until it happens twice in a row. If a cycle
lost interrupt occurs, clear it, and check whether the cycle lost interrupt reoccurs. If another
cycle lost interrupt does not occur, it was probably a false cycle lost condition. If another cycle
lost interrupt does occur then the node should participate to the extent it can in the selection
of a new cyclemaster. These conditions are unlikely to occur; it is not thought this presents
a significant problem for users.
If a legitimate, single event, cycle lost interrupt occurs, an MPEG isochronous packet to be
transmitted may have become stale and should not be sent. If an MPEG packet has been
held in the transmit FIFO during the lost cycle, it can be checked by link layer logic (the MPEG
aging logic) to determine if the data is stale (too late) and should not be sent. No other type
of IEC 61883 isochronous data requires “l(fā)ate” packets to not be sent.
6.3.1
Operating ceLynx in manual cycle master mode (LCTRL.CMAUTO = 0) results in two cycle
masters on the bus in some topology configurations.
Workaround: Do not use manual cycle mater mode. Application should use cycle master
auto mode by setting LCTRL.CMAUTO bit to 1 during initialization phase. The cycle master
auto mode automatically sets LCTRL.CYCMASTER to 1 and enables the cycle master func-
tion when the node becomes root.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB42AA9IPZT | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| TSB42AB4I | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB43AA82A1 | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| TSB81BA3I | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB42AA9IPZT | 功能描述:IC 1394 STORAGELYNX 100-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| TSB42AA9PZT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB42AA9PZTR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| TSB42AB4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
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