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參數(shù)資料
| 型號： | TSB21LV03BI |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394-1995 Triple-Cable Transceiver/Arbiter(IEEE1394-1995 三電纜收發(fā)器/判優(yōu)器) |
| 中文描述： | 電機及電子學(xué)工程師聯(lián)合會1394-1995三線收發(fā)器/仲裁器（IEEE1394連接- 1995三電纜收發(fā)器/判優(yōu)器） |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 351K |
| 代理商： | TSB21LV03BI |
TSB21LV03BI
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SGLS108 – FEBRUARY 1999
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
LREQ
TYPE
I/O
DESCRIPTION
NO.
3
CMOS
I
Link request. LREQ is an input from the LLC that requests the TSB21LV03B to perform
some service. LREQ is 5-V tolerant and has an internal bushold function built-in. If this
terminal is tied through a resistor to a fixed state, the resistor must be 1 k
or less.
PC2 – PC0
28, 29, 30
CMOS
I
Power class indicators. The PC signals set the bit values of the three power-class bits in the
Self-ID packet (bits 21, 22, and 23). These bits can be programmed by tying the terminals to
VDD (high) or to GND (low).
Power down. When asserted high, PD turns off all internal circuitry except the CNA monitor
circuits that drive the CNA terminal. PD is 5-V tolerant. The PD terminal may be tied directly
to VDD or to DGND. If this terminal is tied through a resistor to a fixed state, the resistor must
be 1 k
or less. The PD terminal has an internal bushold function built into it.
PLL circuit ground. The PLLGND terminals should be tied to the low-impedance circuit-board
ground plane. External to the device, AGND should be tied to DGND and PLLGND.
PD
7
CMOS
I
PLLGND
52, 53
Supply
—
PLLVDD
58
Supply
—
PLL circuit power. PLLVDD supplies power to the PLL portion of the device. It is recom-
mended that a combination of high-frequency decoupling capacitors be connected to
PLLVDD (i.e., paralleled 0.1
μ
F and 0.001
μ
F). Lower frequency 10-
μ
F filtering capacitors
can also be used. The PLLVDD supply terminals are separated from AVDD and DVDD inter-
nally in the device to provide noise isolation. The PLLVDD, AVDD, and DVDD terminals should
also be tied together to a power plane on the circuit board. Individual filtering networks for
each are recommended.
R0
R1
59
60
—
—
Current setting resistor. An internal reference voltage is applied to a resistor connected be-
tween R0 and R1 to set the operating current and the cable driver output current. A low tem-
perature-coefficient resistor (TCR) 6.3 k
±
0.5% resistor should be used to meet the IEEE
1394-1995 standard requirements for output voltage limits.
RESET
1
CMOS
I
Reset. When RESET is asserted low (active), a bus reset condition is set on the active cable
ports and the the internal logic is reset to the reset start state. An internal pullup resistor,
which is connected to VDD, is provided so only an external delay capacitor is required. This
input is a standard logic buffer and can also be driven by an open-drain logic output buffer.
The minimum hold time for RESET is listed in the recommended operating characteristics
table.
SYSCLK
9
CMOS
O
System clock. SYSCLK provides a 49.152-MHz clock signal, which is synchronized with the
data transfers to the LLC.
TESTM1
TESTM2
22
21
CMOS
I
Test mode control. TESTM1 and TESTM2 are used during the manufacturing test and
should be tied to VDD.
TPA1+
TPA2+
TPA3+
45
40
36
Cable
O
Portn, port cable pair A. TPAn is the port A connection to the twisted-pair cable. Board traces
from these terminals should be kept matched and as short as possible to the external load
resistors and to the cable connector.
TPA1–
TPA2–
TPA3–
44
39
35
TPB1+
TPB2+
TPB3+
43
38
34
Cable
O
Portn, port cable pair B. TPBn is the port B connection to the twisted-pair cable. Board traces
from these terminals should be kept matched and as short as possible to the external load
resistors and to the cable connector.
TPB1–
TPB2–
TPB3–
42
37
33
TPBIAS1
TPBIAS2
TPBIAS3
46
47
48
Cable
O
Portn, twisted-pair bias. TPBIASn provides the 1.86-V nominal bias voltage needed for prop-
er operation of the twisted-pair cable drivers and receivers and for sending a valid cable
connection signal to the remote nodes.
VDD–5V
4
Supply
—
5-V VDD supply. VDD–5V should be connected to the LLC VDD supply when a 5-V LLC is
connected to the phy, and it should be connected to the phy DVDD when a 3-V LLC is used.
Crystal oscillator. XO and XI connect to a 24.576-MHz parallel resonant fundamental mode
crystal. Although, when a 24.576-MHz crystal oscillator is used, it can be connected to XI
with XO left unconnected. The optimum values for the external shunt capacitors are depen-
dent on the specifications of the crystal used. The suggested values of 12 pF are appropriate
for a crystal with 15-pF specified loads.
XI
XO
56
57
—
—
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB21LV03C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB21LV03CHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB21LV03CMHV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB21LV03CMHVB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB21LV03CPM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
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