參數(shù)資料
型號(hào)： TSB21LV03BI
廠商： Texas Instruments, Inc.
英文描述： IEEE 1394-1995 Triple-Cable Transceiver/Arbiter(IEEE1394-1995 三電纜收發(fā)器/判優(yōu)器)
中文描述： 電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995三線收發(fā)器/仲裁器（IEEE1394連接- 1995三電纜收發(fā)器/判優(yōu)器）
文件頁(yè)數(shù)： 12/25頁(yè)
文件大小： 351K
代理商： TSB21LV03BI
TSB21LV03BI
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SGLS108 – FEBRUARY 1999
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
internal register configuration
The accessible internal registers of this device are listed in Table 1.
Table 1. Internal Register Configuration
Address
0
1
2
3
4
5
6
7
0000
Physical ID
R
CPS
0001
RHB
IBR
GC
0010
SPD
Rev
NP
0011
AStat1
BStat1
Ch1
Con1
Reserved
0100
AStat2
BStat2
Ch2
Con2
Reserved
0101
AStat3
BStat3
Ch3
Con3
Reserved
0110
LoopInt
CPSInt
CPS
IR
Reserved
C
0111
Reserved
1000
Reserved
Table 2. Internal Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
ááááááááá
á
á
á
á
á
á
á
á
áááááááá
ááá
ááá
ááá
ááá
áááááááá
ááá
ááá
ááá
ááá
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Read
only
AStat contains the line state of TPAn. The status is indicated by the following:
11 = high-impedance state
01 = 1
10 = 0
00 = Invalid data state. Power-up reset initializes to this line state. This line state is also output during
transmit and receive operations, including date-end signaling. The line state outputs are generally valid
during arbitration and idle conditions on the bus.
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Read
only
BStat contains the line state of TPBn. The status is indicated by the following:
11 = high-impedance state
01 = 1
10 = 0
00 = Invalid data state. Power-up reset initializes to this line state. This line state is also output during
transmit and receive operations. The line state outputs are generally valid during arbitration and idle
conditions on the bus.
Bus manager capable. C indicates the state of the Bus Manager Capable input. When set, this bit is used
by the TSB21LV03B to specify in the Self-ID packet that the node is Bus Manager Capable.
ááááááááá
á
á
á
á
á
á
á
áááááááá
ááá
Ch(n)
áááááááá
ááá
ááá
ááá
ááá
ááá
ááá
á
á
á
á
á
á
1
á
á
á
Read
When Ch = 1, the port is a child, otherwise it is a parent. This bit is invalid after a hardware reset or a bus
reset until tree-ID processing is completed.
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Read
only
Con indicates the connection status of the port. When Con = 1, the port is connected, otherwise it is
disconnected. This bit is set to 1 by a hardware reset and is updated to reflect the actual cable connection
status of the port during bus reset. The TSB21LV03B contains connection debounce circuitry that prevents
a new cable connection on a port from initiating a bus reset until the connection status has been stable for
at least 335 ms. A cable disconnect initiates a bus reset immediately. After a hardware reset, the
TSB21LV03B sets the connection status of all ports to 0. The TSB21LV03B proceeds with the bus reset,
tree-ID, and Self-ID, but with all ports considered to be disconnected child ports. The TSB21LV03B can not
transmit any signals on the serial bus ports during this time. The TSB21LV03B does report itself as root
with a physical address of 00h at the completion of Self-ID. If any port is actually connected, after the
debounce delay, the TSB21LV03B initiates another bus reset, which proceeds normally with interaction
between the TSB21LV03B and its peer nodes.
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TSB21LV03C 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
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