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參數(shù)資料
| 型號： | TSB21LV03BI |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394-1995 Triple-Cable Transceiver/Arbiter(IEEE1394-1995 三電纜收發(fā)器/判優(yōu)器) |
| 中文描述： | 電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995三線收發(fā)器/仲裁器（IEEE1394連接- 1995三電纜收發(fā)器/判優(yōu)器） |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 351K |
| 代理商： | TSB21LV03BI |
TSB21LV03BI
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SGLS108 – FEBRUARY 1999
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 2. Internal Register Field Descriptions (continued)
DESCRIPTION
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Cable power status (CPS) contains the status of the CPS input terminal. When cable power voltage has
dropped too low for reliable operation, CPS is reset (0). CPS is included twice in the internal registers to
expedite handling of the CPSInt.
CPSInt
1
Read/
Write
CPSint indicates that a cable power status interrupt has occurred. This interrupt occurs whenever the CPS
input goes low. The interrupt indicates that the cable power voltage has dropped too low to ensure reliable
operation. This bit is cleared (0) by a hardware reset or by writing a 0 to this register. However, if the CPS input
is still low, another cable-power status interrupt immediately occurs.
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IBR
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Read/
Write
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Read/
Write
The gap count (GC) register sets the fair and arb-reset gap times. The gap count may be set to a particular
value to optimize bus performance. Typically, the gap count should be set to 2 times the maximum number
of hops on the bus and
must
be set to the same value for all nodes on the bus. The gap count can be set
by either a write to this register or by reception or transmission of a PHY_CONFIG packet. The gap count
is reset to 3Fh after a hardware reset or after two consecutive bus resets without an intervening write to
the gap count register (either a write to the gap count register by the LLC or a PHY_CONFIG packet).
When set, initiate bus reset (IBR) causes the current node to immediately initiate a bus reset. IBR is
cleared (0) after a hardware reset or a bus reset.
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Read/
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IR indicates that the last bus reset was initiated in this TSB21LV03B phy. This bit is also included in the
Self-ID packet.
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Read/
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LoopInt indicates that a configuration loop timeout has occurred. This interrupt occurs when the arbitration
controller waits for too long a period of time during tree-ID. This interrupt can indicate that the bus is
configured in a loop. This bit is cleared (0) by a hardware reset or by writing a 0 to this register bit.
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NP contains the number of ports implemented in the core logic (not the number of ports actually on the
device). For the TSB21LV03B, NP is set to 0011b.
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R
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Physical ID contains the physical address of the local node. The physical ID in valid after a hardware reset
or a bus reset until the Self-ID process has been completed. A complete Self-ID is indicated by an
unsolicited status transfer of the register 0 contents to the LLC.
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Read
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R indicates whether the current node is the root node or not. This bit is cleared (0) on a hardware reset or
a bus reset. This bit is set during tree-ID when the current node is root.
The revision (Rev) bits indicate the design revision of the core logic. For the TSB21LV03B, Rev is set to
00.
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Read/
When set, the root hold-off bit (RHB) instructs the local node to try to become the root node during the next
bus reset. RHB is reset (0) during a hardware reset and is not affected by a bus reset.
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The speed (SPD) bits indicates the top signaling speed of the local port and for the TSB21LV03B is set to
01b.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB21LV03C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB21LV03CHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB21LV03CMHV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB21LV03CMHVB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB21LV03CPM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
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