參數(shù)資料
型號(hào): TSB21LV03BI
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394-1995 Triple-Cable Transceiver/Arbiter(IEEE1394-1995 三電纜收發(fā)器/判優(yōu)器)
中文描述: 電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995三線收發(fā)器/仲裁器(IEEE1394連接- 1995三電纜收發(fā)器/判優(yōu)器)
文件頁數(shù): 19/25頁
文件大?。?/td> 351K
代理商: TSB21LV03BI
TSB21LV03BI
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SGLS108 – FEBRUARY 1999
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Read/Write Requests
When the LLC requests to read the specified register contents, the phy sends the contents of the register to the
LLC through a status transfer. When an incoming packet is received while the phy is transferring status
information to the LLC, the phy continues to attempt to transfer the contents of the register until it is successful.
For write requests, the phy loads the data field into the appropriately addressed register as soon as the transfer
has been completed. The LLC is allowed to request read or write operations at any time.
Status
A status transfer is initiated by the phy when it has status information to transfer to the LLC. The phy waits until
the interface is idle before starting the transfer. The transfer is initiated by asserting the following on the control
terminals: CTL0 – CTL1 = 01 along with the first two bits of status information on the D0 – D3 terminals. The
phy maintains CTL0 – CTL1 = 01 for the duration of status transfer. The phy may prematurely end a status
transfer by asserting something else other than CTL0 – CTL1 = 01 on the control terminals. This could be caused
by an incoming packet from another node. The phy continues to attempt to complete the transfer until the
information has been successfully transmitted. There must be at least one idle cycle in between consecutive
status transfers.
The phy normally sends just the first 4 bits of status to the LLC. These bits are status flags that are needed by
the LLC state machines. The phy sends an entire status packet to the LLC after a request transfer that contains
a read request, or when the phy has pertinent information to send to the LLC or transaction layers. The only
defined condition where the phy automatically sends a register to the LLC is after Self-ID, when it sends the
physical-ID register, which contains the new node address. After a power-on reset, the TSB21LV03B sends two
Self-ID status transfers. The first transfer is invalid (a status of not connected); later, during the same bus reset,
a second, correct Root, Node Number, and connection status Self-ID is transferred. During all other bus resets,
only one SElf-ID status is transmitted.
The definition of the bits in the status transfer are shown in Table 10 and the timing is shown in Figure 7.
Table 10. 16-Bit Stream Status Request
BIT(S)
NAME
DESCRIPTION
0
Arbitration reset gap
Bit 0 indicates that the phy has detected that the bus has been idle for an arbitration reset gap time
(this time is defined in the IEEE 1394–1995 standard). Bit 0 is used by the LLC in its busy/retry
state machine.
1
Subaction gap
Bit 1 indicates that the phy has detected that the bus has been idle for a subaction gap time (this
time is defined in the IEEE 1394–1995 standard). Bit 1 is used by the LLC to detect the completion
of an isochronous cycle.
2
Bus reset
Bit 2 indicates that the phy has entered the bus reset state.
3
State timeout or CPS
Bit 3 indicates that the phy stayed in a particular state for too long a period, which is usually the
effect of a loop in the cable topology, or that the cable power has dropped below the threshold for
reliable operation.
4–7
Address
Bits 4 – 7 hold the address of the phy register whose contents are transferred to the LLC.
8–15
Data
Bits 8 – 15 contain the data that is to be sent to the LLC.
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