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參數(shù)資料
| 型號： | TSB21LV03BI |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394-1995 Triple-Cable Transceiver/Arbiter(IEEE1394-1995 三電纜收發(fā)器/判優(yōu)器) |
| 中文描述： | 電機及電子學工程師聯(lián)合會1394-1995三線收發(fā)器/仲裁器（IEEE1394連接- 1995三電纜收發(fā)器/判優(yōu)器） |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 351K |
| 代理商： | TSB21LV03BI |
TSB21LV03BI
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SGLS108 – FEBRUARY 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
AGND
TYPE
I/O
DESCRIPTION
NO.
26, 32, 41,
49, 50, 61
Supply
—
Analog circuit ground. All AGND terminals should be tied together to the low-impedance
circuit-board ground plane. External to the device, AGND should be tied to DGND and
PLLGND.
AVDD
24, 25,
51, 55
Supply
—
Analog circuit power.
A combination of high frequency decoupling capacitors near each
AVDD terminal is suggested, such as 0.1-
μ
F and 0.001-
μ
F capacitors. Lower frequency
10-
μ
F filtering capacitors are also recommended. AVDD terminals are separated from
DVDD terminals internally from the other supply terminals to provide noise isolation. They
should be tied together to a power plane on the circuit board. Each supply source should
be individually filtered.
Bus manager capable (input). When set as an input, C/LKON specifies in the Self-ID
packet that the node is bus manager capable. The bit value programming is done by tying
the terminal through a 10-k
resistor to VDD (high, bus manager capable) or to GND (low,
not bus manager capable). Using either the pullup or pulldown resistor allows the link-on
output to override the input bit value when necessary.
C/LKON
27
CMOS
I/O
Link-on (output). When set as an output, C/LKON indicates the reception of a link-on
message by asserting a 6.114-MHz signal.
CNA
31
CMOS
O
Cable-not-active output. CNA is asserted high when none of the TSB21LV03B ports are
connected to another active port. This circuit remains active during the power-down mode.
CPS
23
CMOS
I
Cable power status. CPS is normally connected to the cable power through a 400-k
resistor. This circuit drives an internal comparator that detects the presence of cable power.
This information is maintained in two internal registers and is available to the LLC by way
of a register read (see the Phy-Link Interface Annex in the IEEE 1394-1995 standard).
CTL0
CTL1
11
12
CMOS
I/O
Control I/O. The CTLn terminals are bidirectional communications control signals between
the TSB21LV03B and the LLC. These signals control the passage of information between
the two devices. Control I/O terminals are 5-V tolerant. The CTLn terminals have an
internal bushold function built-in.
D0 – D3
13, 14,
15, 16
CMOS
I/O
Data I/O. The D terminals are bidirectional and pass data between the TSB21LV03B and
the LLC. Data I/O terminals are 5-V tolerant. The D terminals have an internal bushold
function built-in.
DGND
8, 10, 17,
18, 63, 64
Supply
—
Digital circuit ground. The DGND terminals should be tied to the low-impedance
circuit-board ground plane. External to the device, AGND should be tied to DGND and
PLLGND.
DVDD
5, 6,
19, 20
Supply
—
Digital circuit power.
DVDD supplies power to the digital portion of the device. It is
recommended that a combination of high-frequency decoupling capacitors be connected to
DVDD (i.e., paralleled 0.1
μ
F and 0.001
μ
F). Lower frequency 10-
μ
F filtering capacitors can
also be used. These supply terminals are separated from AVDD internally to provide noise
isolation. These terminals should also be tied together to a power plane on the circuit
board. Individual filtering networks for each is desired.
PLL filter. FILTER is connected to a 0.1-
μ
F capacitor and then to PLLGND to complete the
internal lag-lead filter. This filter is required for stable operation of the frequency multiplier
PLL running off of the crystal oscillator.
FILTER
54
CMOS
I/O
ISO
62
CMOS
I
Link interface isolation input. ISO is normally tied high both to implement TI bus-holder
isolation and for normal isolation. The TSB21LV03B does not support Annex J isolation.
LPS
2
CMOS
I
Link power status. LPS is connected to either the VDD supplying the LLC through a 1–k
resistor or directly to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. The pulsed signal must be between 220 kHz
and 5.5 MHz to be sensed as active. If LPS is inactive, the phy-LLC interface is disabled,
and the TSB21LV03B performs only the basic repeater functions required for network
initialization and operation. LPS is 5-V tolerant and has an internal bushold function built-in.
If this terminal is tied through a resistor to a fixed state, the resistor must be 1 k
or less.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB21LV03C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB21LV03CHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB21LV03CMHV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB21LV03CMHVB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB21LV03CPM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
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