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參數(shù)資料
| 型號： | TSB21LV03BI |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394-1995 Triple-Cable Transceiver/Arbiter(IEEE1394-1995 三電纜收發(fā)器/判優(yōu)器) |
| 中文描述： | 電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995三線收發(fā)器/仲裁器（IEEE1394連接- 1995三電纜收發(fā)器/判優(yōu)器） |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 351K |
| 代理商： | TSB21LV03BI |
TSB21LV03BI
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SGLS108 – FEBRUARY 1999
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The TSB21LV03B is designed to operate with an LLC such as the TI TSB12LV21A, TSB12LV31, and
TSB12C01A. These devices use an interface as described in Annex J of the IEEE 1394-1995 standard. Details
of how the TSB12LV21A, TSB12LV31, and TSB12C01A LLC devices operate are described in the LLC data
sheets (i.e.,TSB12LV21A, TSB12LV31, and TSB12C01A). The following paragraphs describe the operation of
the phy-LLC interface.
The TSB21LV03B supports 100-/200-Mbit/s data transfer and has four bidirectional data lines, D0 – D3,
crossing the interface. In 100-Mbit/s operation only D0 and D1 terminals are used. In 200 Mbit/s operation, all
Dn terminals are used for data transfer. The unused Dn terminals are driven low. In addition, there are two
bidirectional control lines CTL0 and CTL1, the 50-MHz SYSCLK line from the phy to the LLC, and the LLC
request terminal LREQ from the LLC to the phy. The TSB21LV03B has control of all bidirectional terminals. The
LLC is allowed to drive these terminals only after it has been given permission by the phy. The dedicated LREQ
request terminal is used by the LLC for any activity that it wishes to initiate.
There are four operations that may occur in the phy-LLC interface: request, status, transmit, and receive. With
the exception of the request operation, all actions are initiated by the phy.
When the phy has control of the bus the CTL0 and CTL1 lines are encoded as shown in Table 3.
Table 3. CTLn Status When Phy Has Control of the Bus
CTL0
CTL1
STATUS NAME
DESCRIPTION
0
0
Idle
No activity is occurring (this is the default mode).
0
1
Status
Status information is being sent from the phy to the LLC.
1
0
Receive
An incoming packet is being sent from the phy to the LLC.
1
1
Transmit
The LLC has been given control of the bus to send an outgoing packet.
When the LLC has control of the bus (phy permission) the CTL0 and CTL1 terminals are encoded as shown
in Table 4.
Table 4. CTLn Status When LLC Has Control of the Bus
CTL0
CTL1
STATUS NAME
DESCRIPTION
0
0
Idle
The LLC releases the bus (transmission has been completed).
0
1
Hold
The LLC is holding the bus while data is being prepared for transmission or is sending another packet
without arbitrating.
1
0
Transmit
An outgoing packet is being sent from the LLC to the phy.
1
1
Reserved
None
Request
When the LLC requests the bus or accesses a register that is located in the TSB21LV03B, a serial stream of
information is sent across the LREQ line. The length of the stream varies depending on whether the transfer
is a bus request, a read command, or a write command. Regardless of the type of transfer, a start bit of 1 is
required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. Bit 0 is the most
significant bit and is transmitted first. The LREQ terminal is required to idle low (logic level 0).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB21LV03C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB21LV03CHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB21LV03CMHV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB21LV03CMHVB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB21LV03CPM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
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