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參數(shù)資料
| 型號(hào)： | TPS2306EVM-001 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | TPS2306 Dual Sequencing Hot Swap Power Manager Evaluation Module and Interface Card(雙序列熱交換電源管理器件TPS2306的評(píng)估板與接口卡) |
| 中文描述： | TPS2306熱插拔雙測(cè)序電源管理評(píng)估模塊和接口卡（雙序列熱交換電源管理器件TPS2306的評(píng)估板與接口卡） |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大?。?/td> | 462K |
| 代理商： | TPS2306EVM-001 |
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SLUU094
12
TPS2306 Dual Sequencing Hot Swap Power Manager
3.2.2
Functional Test
Verify the two power supplies are ON. On the hot swap EVM, verify that the red
FAULT
LED is ON. Using the
DVM, verify that both outputs at TP3 and TP4 are OFF (0 volts present).
Set the oscilloscope to trigger on the rising edge of the ENABLE signal on scope Channel 1. Set the trigger mode
to NORMAL. On the interface card, place switch S1 in the HI position. Verify a scope sweep is obtained which
is similar to the one shown in Figure 6. The total ramp time of the two output voltages, from the start of V
OUT1
to V
OUT2
attaining the input dc level, should be approximately 2.1 ms.
tSTART
VOUT2
VOUT1
ENABLE
Figure 6. Output Start-Up Waveforms
Verify the red LED is off. At test points TP3 (V
OUT1
) and TP4 (V
OUT2
) verify that the input supply potential is
present.
On the interface card, set switch S1 to the LO position. Verify that the two output node voltages decay to 0 volts.
NOTE:
Due to the amount of capacitance present at the EVM board outputs, the output decay will
be very slow.
NOTE:
In the following procedure step, if the EVM LED turns OFF, the interface card S1 switch
should be returned to the LO position without unnecessary delay. This will prevent excessive
temperature rise in the interface card and EVM UUT, and possible subsequent damage to the
boards.
Move the scope channel 3 probe to test point TP10 on the hot swap EVM. Connect a shorting jumper between
banana jacks J2 and J3 on the EVM. On the interface card, place switch S1 in the HI position. Verify that the
EVM red
FAULT
LED remains ON.
Verify a scope sweep was obtained similar to the one shown in Figure 7. The time t
1
in the figure should be
approximately 4.84 ms. Verify the EVM outputs are OFF (0 volts present at J1 (TP3) and J3 (TP4)).
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