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6.19 Timers
6.19.1
Timer Peripheral Register Description(s)
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
The DM6437 device has 3 64-bit general-purpose timers which have the following features:
64-bit count-up counter
Timer modes:
–
64-bit general-purpose timer mode (Timer 0 and 1)
–
Dual 32-bit general-purpose timer mode (Timer 0 and 1)
–
Watchdog timer mode (Timer 2)
2 possible clock sources:
–
Internal clock
–
External clock input via timer input pin TINPL (Timer 0 and 1 only)
2 operation modes:
–
One-time operation (timer runs for one period then stops)
–
Continuous operation (timer automatically resets after each period)
Generates interrupts to the DSP
Generates sync event to EDMA
Causes device global reset upon watchdog timer timeout (Timer 2 only)
For more detailed information, see
Section 2.9
,
Documentation Support
for the
TMS320DM643x DMP
64-Bit Timer
User's Guide (literature number SPRU989).
Table 6-92. Timer 0 Registers
HEX ADDRESS RANGE
0x01C2 1400
0x01C2 1404
0x01C2 1410
0x01C2 1414
0x01C2 1418
0x01C2 141C
0x01C2 1420
0x01C2 1424
0x01C2 1428 - 0x01C2 17FF
ACRONYM
-
EMUMGT_CLKSPD
TIM12
TIM34
PRD12
PRD34
TCR
TGCR
-
DESCRIPTION
Reserved
Timer 0 Emulation Management/Clock Speed Register
Timer 0 Counter Register 12
Timer 0 Counter Register 34
Timer 0 Period Register 12
Timer 0 Period Register 34
Timer 0 Control Register
Timer 0 Global Control Register
Reserved
Table 6-93. Timer 1 Registers
HEX ADDRESS RANGE
0x01C2 1800
0x01C2 1804
0x01C2 1810
0x01C2 1814
0x01C2 1818
0x01C2 181C
0x01C2 1820
0x01C2 1824
0x01C2 1828 - 0x01C2 1BFF
ACRONYM
-
EMUMGT_CLKSPD
TIM12
TIM34
PRD12
PRD34
TCR
TGCR
-
DESCRIPTION
Reserved
Timer 1 Emulation Management/Clock Speed Register
Timer 1 Counter Register 12
Timer 1 Counter Register 34
Timer 1 Period Register 12
Timer 1 Period Register 34
Timer 1 Control Register
Timer 1 Global Control Register
Reserved
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Peripheral Information and Electrical Specifications
283