參數(shù)資料
型號： TLIU04C1
英文描述： TLIU04C1 Quad T1/E1 Line Interface
中文描述： TLIU04C1四T1/E1線路接口
文件頁數(shù)： 78/100頁
文件大小： 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
78
Lucent Technologies Inc.
Direct Logic Control Mode
(continued)
Output Pulse Generation
The transmitter accepts a clock with NRZ data in single-rail mode (DUAL = 0) or a clock with positive and negative
NRZ data in dual-rail mode (DUAL = 1) from the system. The device converts this data to a balanced bipolar signal
(AMI format) with optional B8ZS(DS1)/HDB3(CEPT) encoding and jitter attenuation. Low-impedance output drivers
produce these pulses on the line interface. Positive ones are output as a positive pulse on TTIP and negative ones
are output as a positive pulse on TRING. Binary zeros are converted to null pulses. The total delay of the data from
the system interface to the transmit driver is approximately 3 to 11 bit periods, depending on the code configuration
(see the Clock/Data Recovery Mode (CDR) section, page 69 and the Zero Substitution Encoding (CODE) section,
page 79).
Additional delay results if the jitter attenuator is selected for use in the transmit path (see the LIU Delay Values sec-
tion).
Transmit pulse shaping is controlled by the on-chip pulse-width controller and pulse equalizer. The pulse-width con-
troller produces high-speed timing signals to accurately control the transmit pulse widths. This eliminates the need
for a tightly controlled transmit clock duty cycle that is usually required in discrete implementations. The pulse
equalizer controls the amplitudes of the pulses. Different pulse equalizations are selected through proper settings
of the EQA, EQB, and EQC pins as described in Table 45.
Table 45. Equalizer/Rate Control
* In DS1 mode, the distance to the DSX for 22 gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types.
In CEPT mode, equalization is specified for coaxial or twisted-pair cable.
Loss measured at 772 kHz.
In 75
applications, Option 1 is recommended over Option 2 for lower device power dissipation. Option 2 allows for the same transformer as
used in CEPT 120
applications.
Jitter
The intrinsic jitter of the transmit path, i.e., the jitter at TTIP/TRING when no jitter is applied to TCLK (and the jitter
attenuator is not selected, JAT = 0), is typically 5 nsp-p and will not exceed 0.02 UIp-p.
EQA
EQB
EQC
Service
Clock
Rate
Transmitter Equalization
*
Maximum
Cable Loss
Feet
Meters
dB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DS1
1.544 MHz
0 ft. to 131 ft.
131 ft. to 262 ft.
262 ft. to 393 ft.
393 ft. to 524 ft.
524 ft. to 655 ft.
0 m to 40 m
40 m to 80 m
80 m to 120 m
120 m to 160 m
160 m to 200 m
0.6
1.2
1.8
2.4
3.0
—
—
—
CEPT
2.048 MHz
75
(Option 2)
120
or 75
(Option 1)
—
Not Used
—
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