參數(shù)資料
型號： TLIU04C1
英文描述： TLIU04C1 Quad T1/E1 Line Interface
中文描述： TLIU04C1四T1/E1線路接口
文件頁數(shù)： 62/100頁
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
62
Lucent Technologies Inc.
Direct Logic Control Mode
(continued)
Pin Information
(continued)
Table 39. Pin Descriptions
* I = input, O = output, I
u
indicates an input with internal pull-up; I
d
indicates an input with internal pull-down, P = power. Resistance value of all
internal pull-ups or pull-downs is 50 k
, unless otherwise specified.
Pin
Symbol
Type
*
I
d
Qty
Name/Description
117
CLKS
1
XCLK Select.
This pin selects either a 16x line rate clock for XCLK
(CLKS = 0) or a primary line rate clock for XCLK (CLKS = 1).
XCLK Mode.
This pin sets the mode when using a primary line rate
clock for XCLK.
CEPT: CLKM = 1
DS1:
CLKM = 0
Power Supply for Line Drivers.
The device requires a 5 V
±
5%
power supply on these pins.
Ground Reference for Line Drivers.
116
CLKM
I
d
1
130, 27,
58, 99
128, 132,
25, 29,
56, 60,
97, 101
129, 28,
57, 100
131, 26,
59, 98
133, 24,
61, 96
136, 21,
64, 93
134, 23,
62, 95
135, 22,
63, 94
142, 15,
70, 87
141, 16,
69, 88
V
DDX
[1—4]
P
4
GND
X
[1—4]
P
8
TTIP[1—4]
O
4
Transmit Bipolar Tip.
Positive bipolar transmit data to the analog
line interface.
Transmit Bipolar Ring.
Negative bipolar transmit data to the
analog line interface.
Power Supply for Analog Circuitry.
The device requires a
5 V
±
5% power supply on these pins.
Ground Reference for Analog Circuitry.
TRING[1—4]
O
4
V
DDA
[1—4]
P
4
GND
A
[1—4]
P
4
RTIP[1—4]
I
4
Receive Bipolar Tip.
Positive bipolar receive data from the analog
line interface.
Receive Bipolar Ring.
Negative bipolar receive data from the
analog line interface.
Transmit Clock.
DS1 (1.544 MHz
±
32 ppm) or CEPT
(2.048 MHz
±
50 ppm) clock signal from the terminal equipment.
Transmit Data Positive Rail/Transmit Data.
If dual = 0, this pin is
used as 1.544 Mbits/s or 2.048 Mbits/s unipolar input data. If
dual = 1, this pin is used as the transmit data positive rail.
Transmit Data Negative Rail/Substitution Code Enable.
If
dual = 0, this pin is set to insert a B8ZS/HDB3 substitution code
(per EQA, EQB, EQC) on the transmit side and to remove the
substitution code on the receive side. If dual = 1, this pin is used as
the transmit data negative rail.
Receive Clock.
This signal is the receive clock recovered from the
line data. The duty cycle of RCLK is 50%
±
5%.
Receive Data Positive Rail/Receive Data.
If dual = 0, this pin is
used as 1.544 Mbits/s or 2.048 Mbits/s unipolar output data with a
100% duty cycle. If dual = 1, this pin is used to receive data positive
rail.
RRING[1—4]
I
4
TCLK[1—4]
I
4
TPD/
TDATA[1—4]
I
d
4
140, 17,
68, 89
TND/
CODE[1—4]
I
d
4
139, 18,
67, 90
138, 19,
66, 91
RCLK[1—4]
O
4
RPD/
RDATA[1—4]
O
4
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