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參數資料
| 型號： | TLIU04C1 |
| 英文描述： | TLIU04C1 Quad T1/E1 Line Interface |
| 中文描述： | TLIU04C1四T1/E1線路接口 |
| 文件頁數： | 45/100頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TLIU04C1 |
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Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
45
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Registers
(continued)
Alarm Mask Registers (0010, 0011)
The bits in the alarm mask registers in Table 22 allow the microprocessor to selectively mask each channel alarm
and prevent it from generating an interrupt. The mask bits correspond to the alarm status bits in the alarm registers
and are active-high to disable the corresponding alarm from generating an interrupt. These registers are read/write
registers.
*The numerical suffix identifies the channel number.
Global Control Registers (0100, 0101)
The bits in the global control registers in Table 23 and Table 24 allow the microprocessor to configure the various
device functions over all the four channels. All the control bits (with the exception of LOSSTD and ICTMODE) are
active-high. These are read/write registers.
Table 22. Alarm Mask Registers
Bits
Symbol
*
Description
Alarm Mask Register (2)
Mask analog loss of signal alarm for channels 1 and 2.
Mask digital loss of signal alarm for channels 1 and 2.
Mask transmit driver monitor alarm for channels 1 and 2.
Mask loss of transmit clock alarm for channels 1 and 2.
Alarm Mask Register (3)
Mask analog loss of signal alarm for channels 3 and 4.
Mask digital loss of signal alarm for channels 3 and 4.
Mask transmit driver monitor alarm for channels 3 and 4.
Mask loss of transmit clock alarm for channels 3 and 4.
0, 4
1, 5
2, 6
3, 7
MALOS[1—2]
MDLOS[1—2]
MTDM[1—2]
MLOTC[1—2]
0, 4
1, 5
2, 6
3, 7
MALOS[3—4]
MDLOS[3—4]
MTDM[3—4]
MLOTC[3—4]
Table 23. Global Control Register (0100)
Bits
Symbol
Description
Global Control Register (4)
The GMASK bit globally masks all the channel alarms when GMASK = 1, pre-
venting all the receiver and transmitter alarms from generating an interrupt.
GMASK = 1 after a device reset.
The SWRESET provides the same function as the hardware reset. It is used
for device initialization through the microprocessor interface.
The LOSSTD bit selects the conformance protocol for the DLOS receiver
alarm function.
The ICTMODE bit changes the function of the ICT pin. ICTMODE = 0 after a
device reset.
A HIGHZ bit is available for each individual channel. When HIGHZ = 1, the
TTIP and TRING transmit drivers for the specified channel are placed in a
high-impedance state. HIGHZ [1—4] = 1 after a device reset.
0
GMASK
1
SWRESET
2
LOSSTD
3
ICTMODE
4—7
HIGHZ[1—4]
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