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參數(shù)資料
| 型號： | TLIU04C1 |
| 英文描述： | TLIU04C1 Quad T1/E1 Line Interface |
| 中文描述： | TLIU04C1四T1/E1線路接口 |
| 文件頁數(shù)： | 31/100頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TLIU04C1 |
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Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
31
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Transmitter Alarms
(continued)
Transmit Driver Monitor (TDM) Alarm
(continued)
The monitor operates by comparing the line pulses with
the transmit inputs. After 32 transmit clock cycles, the
transmitter is powered up in its normal operating mode.
The drivers attempt to correctly transmit the next data
bit. If the error persists, TDM remains active to elimi-
nate alarm chatter and the transmitter is internally pro-
tected for another 32 transmit clock cycles. This
process is repeated until the error condition is removed
and the TDM alarm is deactivated. The TDM alarm sta-
tus bit will latch the alarm and remain set until being
cleared by a read (clear on read).
The second monitoring function is to indicate periods of
no data transmission. The alarm is set (TDM = 1) when
32 consecutive zeros have been transmitted, and the
alarm condition is cleared on the detection of a single
pulse. Again, the TDM alarm status bit will latch the
alarm and remain set until being cleared by a read
(clear on read). This alarm condition does not alter the
state or functionality of the signal path.
Upon the transition from TDM = 0 to TDM = 1, a micro-
processor interrupt will be generated if the TDM inter-
rupt mask bit (MTDM; registers 2 and 3, bits 2 and 6) is
not set and the GMASK bit (register 4, bit 0) is not set.
A TDM alarm may occur when RLOOP is activated and
deactivated. If the prevent RLOOP alarm bit (PRLALM;
register 12, bit 3) is not set, then RLOOP may activate
an LOTC alarm, which will put the output drivers TTIP
and TRING in a high-impedance state as described in
Loss of Transmit Clock (LOTC) Alarm on page 30. The
high-impedance state of the drivers may, in turn, gener-
ate a TDM alarm. Setting the HIGHZ alarm prevention
PHIZALM = 1 (register 12, bit 4) prevents the TDM
alarm from occurring when the drivers are in a high-
impedance state.
DS1 Transmitter Pulse Template and Specifi-
cations
The DS1 pulse shape template is specified at the DSX
(defined by CB119 and ANSI T1.102) and is illustrated
in Figure 8. The device also meets the pulse template
specified by ITU-T G.703 (not shown).
5-1160(F)r.1
Figure 8. DSX-1 Isolated Pulse Template
Table 14. DSX-1 Pulse Template Corner Points
(from CB119)
Maximum Curve
Minimum Curve
ns
V
ns
V
0
250
325
325
425
500
675
725
1100
1250
—
—
0.05
0.05
0.80
1.15
1.15
1.05
1.05
–0.07
0.05
0.05
—
—
0
350
350
400
500
600
650
650
800
925
1100
1250
–0.05
–0.05
0.50
0.95
0.95
0.90
0.50
–0.45
–0.45
–0.20
–0.05
–0.05
1.0
0.5
0
–0.5
0
250
500
750
1000
1250
TIME (ns)
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