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參數(shù)資料
| 型號： | TLIU04C1 |
| 英文描述： | TLIU04C1 Quad T1/E1 Line Interface |
| 中文描述： | TLIU04C1四T1/E1線路接口 |
| 文件頁數(shù)： | 44/100頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TLIU04C1 |
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Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
44
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Registers
As shown in Table 6 on page 17, the quad LIU registers consist of sixteen 8-bit registers (some of which are
reserved). Register 13 is an index register which must contain the value 00 to access the other 15 LIU registers.
Registers 0 and 1 are the alarm registers used for storing the various device alarm status and are read only. All
other registers are read/write. Registers 2 and 3 contain the individual mask bits for the alarms in registers 0 and 1.
Registers 4 and 5 are designated as the global control registers used to set up the functions for all four channels.
The channel configuration registers in registers 6 through 9 and register 12 are used to configure the individual
channel functions and parameters. Registers 10 and 11 must be cleared by the user after a powerup for proper
device operation; CODE3 and CODE4 may be set as desired. (See Table 26 on page 47.) Register 13 is the global
index register. Registers 14 and 15 are reserved for proprietary functions and must not be addressed during oper-
ation. The following sections describe these registers in detail.
Alarm Registers (0000, 0001)
The bits in the alarm registers represent the status of the transmitter and receiver alarms LOTC, TDM, DLOS, and
ALOS for all four channels as shown in Table 21. The alarm indicators are active-high and automatically clear on a
microprocessor read if the corresponding alarm condition no longer exists. Persistent alarm conditions will cause
the bit to remain set. These are read-only registers.
*The numerical suffix identifies the channel number.
Table 21. Alarm Registers
Bits
Symbol
*
Description
Alarm Register (0)
Analog loss of signal alarm for channels 1 and 2.
Digital loss of signal alarm for channels 1 and 2.
Transmit driver monitor alarm for channels 1 and 2.
Loss of transmit clock alarm for channels 1 and 2.
Alarm Register (1)
Analog loss of signal alarm for channels 3 and 4.
Digital loss of signal alarm for channels 3 and 4.
Transmit driver monitor alarm for channels 3 and 4.
Loss of transmit clock alarm for channels 3 and 4.
0, 4
1, 5
2, 6
3, 7
ALOS[1—2]
DLOS[1—2]
TDM[1—2]
LOTC[1—2]
0, 4
1, 5
2, 6
3, 7
ALOS[3—4]
DLOS[3—4]
TDM[3—4]
LOTC[3—4]
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