參數資料
型號： TLIU04C1
英文描述： TLIU04C1 Quad T1/E1 Line Interface
中文描述： TLIU04C1四T1/E1線路接口
文件頁數： 53/100頁
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
53
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Microprocessor Interface Timing
The I/O timing specifications for the microprocessor interface are given in Table 37 and shown in Figures 15—22.
The microprocessor interface pins use CMOS I/O levels. All outputs, except the address/data bus AD[7:0], are
rated for a capacitive load of 50 pF. The AD[7:0] outputs are rated for a 100 pF load. The minimum read and write
cycle time is 200 ns for all device configurations.
The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 15—22.
Table 37. Microprocessor Interface I/O Timing Specifications
Symbol
Configuration
Parameter
Setup
(ns)
(Min)
—
10
—
10
5
30
—
—
—
—
—
—
—
—
5
10
—
5
—
—
10
—
Hold
(ns)
(Min)
10
—
10
—
—
—
—
—
—
15
5
—
—
5
—
—
5
—
10
—
—
10
Delay
(ns)
(Max)
—
—
—
—
—
—
25
20
50
—
—
20
10
—
—
—
—
—
—
20
—
—
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
Modes 1 and 2
AS Asserted Width
Address Valid to AS Asserted
AS Asserted to Address Invalid
CS Asserted to AS Asserted
R/W Valid to DS Asserted
AS Asserted to DS Asserted
CS Asserted to DTACK High
DS Asserted to DTACK Asserted
DS Asserted to Data Valid
DS Deasserted to CS Deasserted
DS Deasserted to R/W Invalid
DS Deasserted to DTACK Deasserted
CS Deasserted to DTACK High Impedance
DS Deasserted to Data Invalid
R/W Valid to DS Asserted
AS Asserted to DS Asserted
DS Asserted Width
Data Valid to DS Asserted
DS Deasserted to Data Invalid
DS Asserted to DTACK Asserted
Address Valid to AS Asserted
AS Asserted to Address Invalid
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