參數(shù)資料
型號(hào)： TLIU04C1
英文描述： TLIU04C1 Quad T1/E1 Line Interface
中文描述： TLIU04C1四T1/E1線路接口
文件頁(yè)數(shù)： 12/100頁(yè)
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
12
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
* I = input, O = output, I
u
indicates an input with internal pull-up; I
d
indicates an input with internal pull-down, P = power. Resistance value of all
internal pull-ups or pull-downs is 50 k
, unless otherwise specified.
Pin
Symbol
Type
*
Name/Description
112
ALE_AS
I
Address Latch Enable.
If MPMODE = 1 (pin 110), this pin becomes the
address latch enable for the microprocessor. When this pin transitions from
high to low, the address bus inputs are latched into the internal registers.
Address Strobe (Active-Low).
If MPMODE = 0 (pin 110), this pin becomes
the address strobe for the microprocessor. When this pin transitions from
high to low, the address bus inputs are latched into the internal registers.
113
CS
I
u
Chip Select (Active-Low).
This pin is asserted low by the microprocessor to
enable the microprocessor interface. If MPMUX = 1 (pin 108),
CS
can be
externally tied low to use the internal chip selection function. An internal
100 k
pull-up is on this pin.
Interrupt.
This pin is asserted high to indicate an interrupt produced by an
alarm condition in register 0 or 1. The activation of this pin can be masked by
various register bits.
114
INT
O
115
RDY_DTACK
O
Ready.
If MPMODE = 1 (pin 110), this pin is asserted high to indicate the
device has completed a read or write operation. This pin is in a 3-state
condition when CS (pin 113) is high.
Data Transfer Acknowledge (Active-Low).
If MPMODE = 0 (pin 110), this
pin is asserted low to indicate the device has completed a read or write
operation.
1, 12,
37, 48,
73, 84,
109, 120
GND
D
P
Ground Reference for Microprocessor Interface and Digital Circuitry.
2, 11,
47, 74,
83, 119
V
DDD
P
Power Supply for Microprocessor Interface and Digital Circuitry.
The
TLIU04C1 device requires a 5 V ± 5% power supply on these pins.
46
XCLK
I
u
Reference Clock
.
The clock signal used for clock and data recovery and
jitter attenuation. This clock must be ungapped and free of jitter.
For CLKS = 0, a 16x clock (for DS1, XCLK = 24.704 MHz ± 100 ppm and for
CEPT, XCLK = 32.768 MHz ± 100 ppm).
For CLKS = 1, a 1x clock (for DS1, XCLK = 1.544 MHz ± 100 ppm and for
CEPT, XCLK = 2.048 MHz ± 100 ppm).
To meet TBR 12/13 jitter accommodation requirements (JABW0 = 1), clock
tolerances must be ±20 ppm. An internal 100 k
pull-up is on this pin.
Loss of XCLK
.
This pin is asserted high when the XCLK signal (pin 46) is
not present.
45
LOXC
O
44
RESET
I
u
Hardware Reset (Active-Low)
.
If
RESET
is forced low, all internal states in
the line interface paths are reset and data flow through each channel will be
momentarily disrupted. The
RESET
pin must be held low for a minimum of
10 μs.
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