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參數(shù)資料
| 型號： | TLC34076M-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 34/57頁 |
| 文件大小： | 456K |
| 代理商： | TLC34076M-135 |
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2–18
SCLK
Input
SFLAG/NFLAG
register bit 2)
(general-control-
SSRT Enable
BLANK
Figure 2–9. Relationship Between SFLAG/NFLAG, BLANK, and SCLK
If SFLAG/NFLAG is designed as an R-S latch set by split shift-register-transfer timing and reset by BLANK
going high, the delay from BLANK high to SFLAG/NFLAG low cannot exceed one-half of one SCLK cycle;
otherwise, the SCLK generation logic may fail.
If the SSRT function is enabled but SFLAG/NFLAG is held low, SCLK runs as if the SSRT function is
disabled. The SFLAG/NFLAG input is not qualified by the BLANK signal and needs to be held low whenever
an SSRT SCLK pulse is not desired. Refer to Section 2.3.1 and Figures 2–2 through 2–8 for more system
details.
2.9.2
Special Nibble Mode
Special nibble mode is enabled when the SNM bit (bit 3 in the general-control register) is set to 1 and the
SSRT bit (bit 2 in the general-control register) is reset to 0 (see Section 2.11). Special nibble mode provides
a variation of the 4-bit pixel mode with a 16-bit bus width. While all 32 inputs (P<0:31>) are connected as
4 bytes, the 16-bit data bus is composed of the lower or upper nibble of each of the 4 bytes, depending on
the level of the SFLAG/NFLAG input. The pixel data is distributed to 16-bit data bus as shown in Table 2–9.
Table 2–9. Pixel-Data Distribution in Special Nibble Mode
SNM BIT = 1, SSRT BIT = 0
SFLAG/NFLAG = 1
SFLAG/NFLAG = 0
P<7:4>
P<15:12>
P<23:20>
P<31:28>
P<3:0>
P<11:8>
P<19:16>
P<27:24>
The SFLAG/NFLAG value is not latched by the TLC34076M. Therefore, it should stay at the same level
during the whole active display period, changing levels only during the BLANK signal active time. Refer to
Figure 2–10, which is similar to Figure 2–2 except that the BLANK timing reference to SFLAG/NFLAG is
explained. The SFLAG/NFLAG input has to meet the setup time and hold the data long enough to ensure
no pixel data is missed.
Special nibble mode operates at the line frequency when BLANK is active. However, the typical application
of this mode is double frame buffers with a pixel-data width of 4 bits. While one frame buffer is being
displayed on the monitor, the other frame buffer can be used to accept new picture information.
SFLAG/NFLAG is used to indicate which frame buffer is being displayed.
SNM and SSRT must be mutually exclusive. Unpredictable operation occurs if both the SNM and SSRT bits
are set to 1. The multiplex-control register should be set up as shown in Table 2–6 (see Section 2.4.5);
however, the SNM bit takes precedence over the other multiplex-control-register selections. In other words,
if the multiplex-control register is set up for another mode but special nibble mode is still enabled in the
general-control register, the input multiplex circuit takes whatever SCLK divide ratio the multiplex-control
register specifies and performs the nibble operation, causing operational failure.
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| TLC352CDG4 | 功能描述:校驗(yàn)器 IC Dual Low Vltg LinCMOS Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
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