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參數(shù)資料
| 型號： | TLC34076M-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 27/57頁 |
| 文件大?。?/td> | 456K |
| 代理商： | TLC34076M-135 |
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2–11
MODE
MULTIPLEX-CONTROL-REGISTER BITS
DATA BITS
PER
PIXEL
PIXEL BUS
WIDTH
SCLK
DIVIDE
RATIO§
PIXEL-
LATCHING
SEQUENCE
5
0
4
1
3
1
2
1
1
0
0
0
4
8
8
1
1) P<7:0>
0
1
1
1
0
1
8
16
2
1) P<7:0>
2) P<15:8>
0
1
1
1
1
0
8
32
4
1) P<7:0>
2) P<15:8>
3) P<23:16>
4) P<31:24>
5
0
1
1
1
1
1
4
16
4
NFLAG = 0:
1) P<3:0>
2) P<11:8>
3) P<19:16>
4) P<27:24>
NFLAG = 1:
1) P<7:4>
2) P<15:12>
3) P<23:20>
4) P<31:28>
6
See Table 2–7 and Table 2–8
Bits 6 and 7 are don’t carebits.
This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,
often referred to as the number of bit planes. This may be color-palette-address data (modes 0–5) or DAC data
(mode 6).
§The SCLK divide ratio is the number used for the output-clock-selection register. It indicates the number of pixels per
bus load or the number of pixels associated with each SCLK pulse. For example, with a 32-bit pixel bus width and 8 bit
planes, 4 pixels comprise each bus load. The SCLK divide ratio is not automatically set by mode selection, but must
be written to the output-clock-selection register.
For each operating mode, the pixel-latching sequence indicates the sequence in which pixel port or VGA port data are
latched into the device. The latching sequence is initiated by a rising edge on SCLK. For modes in which multiple groups
of data are latched, the SCLK rising edge latches all the groups and the pixel clock shifts them out starting with the
low-numbered group. For example, in mode 3 with a 16-bit pixel bus width, the rising edge of SCLK latches all the data
groups and the pixel clock shifts them out in the order P<3:0>, P<7:4>, P<11:8>, P<15:12>.
#Mode 0 is a VGA pass-through mode.
||Mode 6 is a true-color mode in which 24 bits of color information are transferred directly from the pixel port to the DACs;
overlay is implemented with the remaining 8 bits of the pixel bus. The distribution of pixel-port data to the DACs is as
follows: P<31:24> are passed to the blue DAC, P<23:16> are passed to the green DAC, and P<15:8> are passed to
the red DAC. P<7:0> are used to generate overlay data; this operation can be disabled by either grounding P<7:0> or
by clearing the read mask (see Section 2.4.6).
Mode 5 is special nibble mode, the only mode in which the pixel bus width is not equal to the actual physical width, in
bits, of the pixel bus. In this mode, the pixel bus is physically 32 bits wide; depending on the value of SFLAG/NFLAG,
either the upper or lower nibble of each of the four physical bytes is selected to comprise the 16 bits of pixel data (equal
to four 4-bit pixels).
NOTE: Although leaving unused pins floating does not adversely affect device operation, tying unused pins to GND
lowers power consumption and thus is recommended.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC34077 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
| TLC34077135FN | 制造商:TI 功能描述:* |
| TLC352 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LinCMOSE DUAL DIFFERENTIAL COMPARATOR |
| TLC352CD | 功能描述:校驗器 IC Dual Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應時間: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
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