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參數(shù)資料
| 型號(hào)： | TLC34076M-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 31/57頁 |
| 文件大小： | 456K |
| 代理商： | TLC34076M-135 |
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2–15
functionality is also supported. VCLK is used to clock and synchronize control inputs like HSYNC, VSYNC,
and BLANK.
The pixel data presented at the inputs is latched at the rising edge of SCLK in normal mode or the rising edge
of CLK0 in VGA pass-through mode. Control inputs HSYNC, VSYNC, and BLANK are sampled and latched
at the falling edge of VCLK in normal mode, while HSYNC, VSYNC, and VGABLANK are latched at the rising
edge of CLK0 in VGA pass-through mode. Both data and control signals are lined up at the DAC outputs
to the monitor through the internal pipeline delay, so external glue logic is not required. The outputs of the
DACs are capable of directly driving a 37.5-
load, as in the case of a double-terminated 75-
cable. See
Figures 2–7 and 2–8 for nominal output levels.
2.6.1
The frame-buffer interface (pixel bus) supports both little- and big-endian data formats for all normal
multiplexing and true-color modes of operation. The data-format-mode select is controlled by general-
control-register bit 6 (see 2.11). When GCR bit 6 is set to 0 (default), then the format is set to the little-endian
mode. When GCR bit 6 is set to 1, then the format is set to bIg-endian mode.
Little- and Big-Endian Modes
In a big-endian-mode design, the external VRAM data bus bits must be connected in reverse order to the
TLC34076M pixel bus; i.e., D31 connected to P0, D0 connected to P31, etc. This ensures that the least
significant channel always provides the first pixel to be displayed in the normal multiplexing modes.
2.7
The DAC outputs are controlled by current sources (three for IOG and two each for IOR and IOB) as shown
in Figure 2–6. In the normal case, there is a 7.5-IRE difference between blank and black levels, which is
shown in Figure 2–7. If a 0-IRE pedestal is desired, it can be selected by resetting bit 4 of the general-control
register (see Section 2.11.3). The video output for a 0-IRE pedestal is shown in Figure 2–8.
Analog Output Specifications
IOG
RL
～
15 pF
G <0:7>
BLANK
(IOG only)
SYNC
VAA
Figure 2–6. Equivalent Circuit of the IOG Current Output
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