參數(shù)資料
型號(hào)： TLC34076M-135
廠商： Texas Instruments, Inc.
英文描述： Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式)
中文描述： 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式）
文件頁(yè)數(shù)： 18/57頁(yè)
文件大小： 456K
代理商： TLC34076M-135
2–2
The color-palette RAM access methodology is described in the following two sections and is fully compatible
with the IMSG176/8 and Bt476/8 color palettes.
2.2.1
To load the color-palette RAM, the MPU must first write to the address register (write mode) with the address
where the modification is to start. This action is followed by three successive writes to the palette-holding
register with eight bits each of red, green, and blue data. After the blue data write cycle, the three bytes of
color are concatenated into a 24-bit word and written to the color-palette-RAM location specified by the
address register. The address register then increments to point to the next color-palette-RAM location,
which the MPU may modify by simply writing another sequence of red, green, and blue data bytes. A block
of color values in consecutive locations can be written to by writing the start address and performing
continuous red, green, and blue write cycles until the entire block has been written.
Writing to the Color-Palette RAM
2.2.2
Reading from the color-palette RAM is performed by writing the location to be read to the address register.
This action initiates a transfer from the color-palette RAM into the holding register followed by an increment
of the address register. Three successive MPU reads from the holding register produce red, green, and blue
color data (six or eight bits, depending on the 8/6 mode) for the specified location. Following the blue read
cycle, the contents of the color-palette RAM at the address specified by the address register are copied into
the holding register and the address register is again incremented. As with writing to the color-palette RAM,
a block of color values in consecutive locations may be read by writing the start address and performing
continuous red, green, and blue read cycles until the entire block has been read.
Reading From the Color-Palette RAM
2.2.3
The 8-bit palette-page register provides high-speed color changing by removing the need for color-palette
RAM reloading. When using 1, 2, or 4 bit planes, the additional planes are provided by the palette-page
register; e.g., when using four bit planes, the pixel inputs specify the lower four bits of the color-palette RAM
address with the upper four bits being specified by the palette register. This provides the capability of
selecting from 16 palette pages with only one chip access, thus allowing all the screen colors to be changed
at the line frequency. A bit-to-bit correspondence is used; therefore, in the above configuration, palette-page
register bits 7 through 4 map onto color-palette RAM address bits 7 through 4, respectively. This is listed
in Table 2–2.
Palette-Page Register
Since there is only one bit of overlay data in the 5-5-5 true-color modes, the page register is used to fill the
seven remaining MSBs (same as 1 bit plane in Table 2–2). All 8 bits need to be 0 in order to enable true color.
The additional bits from the palette-page register are inserted before the read mask and hence, are subject
to masking.
Table 2–2. Allocation of Palette-Page-Register Bits
NUMBER OF
BIT PLANES
MSB
COLOR-PALETTE-RAM-ADDRESS BITS
LSB
8
M
M
M
M
M
M
M
M
4
P7
P6
P5
P4
M
M
M
M
2
P7
P6
P5
P4
P3
P2
M
M
1
P7
P6
P5
P4
P3
P2
P1
M
Pn = nth bit from palette page register
M = bit from pixel port
2.3
The TLC34076M provides a maximum of five clock inputs. Three are dedicated to TTL inputs; the other two
can be selected as either one ECL input or two extra TTL inputs. The TTL and ECL inputs can be used for
Input-/Output-Clock Selection and Generation
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