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參數資料
| 型號： | TL16C2552RHB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS |
| 中文描述： | 1.8 V至5 V雙的UART具有16字節(jié)FIFO |
| 文件頁數： | 4/34頁 |
| 文件大?。?/td> | 407K |
| 代理商： | TL16C2552RHB |
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TL16C2552
SLWS163A–SEPTEMBER 2005–REVISED JUNE 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
FN NO.
2 - 6
I/O
DESCRIPTION
NAME
D0-D4
RHB NO.
27 - 31
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first data bit in
a transmit or receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A
and B. A logic low on these pins indicates the modem or data set is powered on and is ready
for data exchange with the UART. The state of these inputs is reflected in the modem status
register (MSR).
Data terminal ready (active low). These outputs are associated with individual UART channels
A and B. A logic low on these pins indicates that theTLl16C2552 is powered on and ready.
These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0
sets the DTR output to low, enabling the modem. The output of these pins is high after writing
a 0 to MCR bit 0, or after a reset.
Signal and power ground.
Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B.
INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in
the interrupt enable register (IER). Interrupt conditions include: receiver errors, available
receiver buffer data, available transmit buffer space or when a modem status flag is detected.
INTA-B are in the high-impedance state after reset.
Read input (active low strobe). A high to low transition on IOR will load the contents of an
internal register defined by address bits A0-A2 onto the TL16C2552 data bus (D0-D7) for
access by an external CPU.
Write input (active low strobe). A low to high transition on IOW will transfer the contents of the
data bus (D0-D7) from the external CPU to an internal register that is defined by address bits
A0-A2 and CSA and CSB
No internal connection
I/O
D5-D7
7 - 9
32, 1, 2
DSRA,
DSRB
–
I
DTRA,
DTRB
37, 27
–
O
GND
12, 22
20
INTA, INTB
34, 17
21, 9
O
IOR
24
14
I
IOW
20
11
I
NC
–
18, 19
Multi-function output. This output pin can function as the OP, BAUDOUT, or RXRDY pin. One
of these output signal functions can be selected by the user programmable bits 1-2 of the
alternate function register (AFR). These signal functions are described as follows:
1.
OP - When OP (active low) is selected, the MF pin is a logic 0 when MCR bit 3 is set to
a logic 1 (see MCR bit 3). MCR bit 3 defaults to a logic 1 condition after a reset or
power-up.
2.
BAUDOUT - When BAUDOUT function is selected, the 16× baud rate clock output is
available at this pin.
3.
RXRDY - RXRDY (active low) is intended for monitoring DMA data transfers.
If it is not used, leave it unconnected.
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset time. See TL16C2552 external
reset conditions for initialization details. RESET is an active-high input.
Ring indicator (active low). These inputs are associated with individual UART channels A and
B. A logic low on these pins indicates the modem has received a ringing signal from the
telephone line. A low to high transition on these input pins generates a modem status
interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR)
Request to send (active low). These outputs are associated with individual UART channels A
and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send.
Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
available. After a reset, these pins are set to high. These pins only affects the transmit and
receive operation when auto RTS function is enabled through the enhanced feature register
(EFR) bit 6, for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to the
2552. During the local loopback mode, these RX input pins are disabled and TX data is
internally connected to the UART RX input internally.
Transmit data. These outputs are associated with individual serial transmit channel data from
the 2552. During the local loopback mode, the TX input pin is disabled and TX data is
internally connected to the UART RX input.
Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level
numbers of spaces available. They go high when the TX buffer is full.
Power supply inputs.
MFA, MFB
35, 19
–
O
RESET
21
12
I
RIA, RIB
43, 31
–
I
RTSA,
RTSB
36, 23
22, 13
O
RXA, RXB
39, 25
24, 15
I
TXA, TXB
38, 26
23, 16
O
TXRDYA,
TXRDYB
V
CC
1, 32
–
O
33, 44
26
I
4
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