參數(shù)資料
型號： TL16C2552RHB
廠商： Texas Instruments, Inc.
英文描述： 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
中文描述： 1.8 V至5 V雙的UART具有16字節(jié)FIFO
文件頁數(shù)： 22/34頁
文件大小： 407K
代理商： TL16C2552RHB
www.ti.com
PRINCIPLES OF OPERATION
Register Selection
TL16C2552
SLWS163A–SEPTEMBER 2005–REVISED JUNE 2006
Table 1. Register Selection
DLAB
(1)
0
0
0
0
X
X
X
X
X
1
1
1
A2
L
L
L
L
L
H
H
H
H
L
L
L
A1
L
L
H
H
H
L
L
H
H
L
L
H
A0
L
H
L
L
H
L
H
L
H
L
H
L
REGISTER
Receiver buffer (read), transmitter holding register (write)
Interrupt enable register
Interrupt identification register (read only)
FIFO control register (write)
Line control register
Modem control register
Line status register
Modem status register
Scratch register
Divisor latch (LSB)
Divisor latch (MSB)
Alternate function register (AFR)
(1)
The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this
bit location (see
Table 4
).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
RESET CONTROL
Master reset
Master reset
RESET STATE
Interrupt enable register
Interrupt identification register
All bits cleared (0 - 3 forced and 4 - 7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits
4 - 5 are permanently cleared
All bits cleared
All bits cleared
All bits, except bit 3, cleared (6 - 7 permanent), MCR
3 set
Bits 5 and 6 are set; all other bits are cleared
Bits 0 - 3 are cleared; bits 4 - 7 are input signals
High
Output buffer enabled
Low
Low
Low
FIFO control register
Line control register
Modem control register
Master reset
Master reset
Master reset
Line status register
Modem status register
TX
INT
Interrupt condition (receiver error flag)
Interrupt condition (received data available)
Interrupt condition (transmitter holding register
empty)
Interrupt condition (modem status changes)
OP
RTS
DTR
Scratch register
Divisor latch (LSB and MSB) registers
Receiver buffer register
Transmitter holding register
RCVR FIFO
XMIT FIFO
Alternate function register (AFR)
Master reset
Master reset
Master reset
Master reset MCR3
Read LSR/MR
Read RBR/MR
Read IR/write THR/MR
Read MSR/MR
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
MR/FCR1 - FCR0/DFCR0
MR/FCR2 - FCR0/DFCR0
Master reset
Low
Low
High
High
No effect
No effect
No effect
No effect
All bits cleared
All bits cleared
All bits cleared
22
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