參數(shù)資料
型號： TL16C2552RHB
廠商： Texas Instruments, Inc.
英文描述： 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
中文描述： 1.8 V至5 V雙的UART具有16字節(jié)FIFO
文件頁數(shù)： 11/34頁
文件大?。?/td> 407K
代理商： TL16C2552RHB
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
BAUD GENERATOR SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature, C
L
= 30 pF (for FN package only)
TL16C2552
SLWS163A–SEPTEMBER 2005–REVISED JUNE 2006
5 V Nominal
PARAMETER
High-level output voltage
(2)
Low-level output voltage
(2)
Input current
TEST CONDITIONS
MIN
TYP
(1)
MAX
UNIT
V
V
μA
V
OH
V
OL
I
I
I
OH
= -4 mA
I
OL
= 4 mA
V
= 5.5 V, V
= 0, V
I
= 0 to 5.5 V, All other
terminals floating
V
= 5.5 V, V
= 0, V
= 0 to 5.5 V, Chip selected in
write mode or chip deselected
V
= 5.5 V, T
= 0°C, RXA, RXB, DSRA, DSRB,
CDA, CDB, CTSA, CTSB, RIA, and RIB at 2 V, All
other inputs at 0.8 V, XTAL1 at 24 MHz, No load on
outputs
4
0.4
10
I
OZ
High-impedance-state output
current
Supply current
±20
μA
I
CC
7.5
mA
C
i(CLK)
C
O(CLK)
C
I
C
O
Clock input impedance
Clock output impedance
Input impedance
Output impedance
15
20
20
30
10
20
pF
pF
pF
pF
V
CC
= 0, V
= 0, f = 1 MHz,
T
A
= 25°C, All other terminals grounded
6
10
(1)
(2)
All typical values are at V
= 5 V and T
= 25°C.
These parameters apply for all outputs except XTAL2.
LIMITS
ALT.
SYMBOL
TEST
PARAMETER
FIGURE
1.8 V
2.5 V
3.3 V
5 V
UNIT
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
w8
Pulse duration, RESET
t
RESET
1
1
1
1
μs
t
w1
Pulse duration, clock high
t
XH
6
40
25
20
18
ns
t
w2
Pulse duration, clock low
t
XL
t
cR
Cycle time, read (t
w7
+ t
d8
+ t
h7
)
RC
8
115
80
62
57
ns
t
cW
Cycle time, write (t
w6
+ t
d5
+ t
h4
)
WC
7
115
80
62
57
ns
t
w6
Pulse duration, IOW or CS
t
IOW
7
80
55
45
40
ns
t
w7
Pulse duration, IOR or CS
t
IOR
8
80
55
45
40
ns
t
SU3
Setup time, data valid before IOW
↑
or CS
↑
t
DS
7
25
20
15
15
ns
t
h4
Hold time, address valid after IOW
↑
or CS
↑
t
WA
7
20
15
10
10
ns
t
h5
Hold time, data valid after IOW
↑
or CS
↑
t
DH
7
15
10
5
5
ns
t
h7
Hold time, data valid after IOR
↑
or CS
↑
t
RA
8
20
15
10
10
ns
t
d5
Delay time, address valid before IOW
↓
or CS
↓
t
AW
7
15
10
7
7
ns
t
d8
Delay time, address valid to IOR
↓
or CS
↓
t
AR
8
15
10
7
7
ns
t
d10
Delay time, IOR
↓
or CS
↓
to data valid
t
RVD
8
C
L
= 30 pF
55
35
25
20
ns
t
d11
Delay time, IOR
↑
or CS
↑
to floating data
t
HZ
8
C
L
= 30 pF
40
30
20
20
ns
t
d12
Write cycle to write cycle delay
7
100
75
60
50
ns
t
d13
Read cycle to read cycle delay
8
100
75
60
50
ns
LIMITS
ALT.
SYMBOL
TEST
PARAMETER
FIGURE
1.8 V
2.5 V
3.3 V
5 V
UNIT
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
w3
Pulse duration, BAUDOUT low
t
LW
6
CLK ÷ 2
80
50
42
35
ns
t
w4
Pulse duration, BAUDOUT high
t
HW
6
CLK
÷
2
80
50
42
35
ns
t
d1
Delay time, XIN
↑
to BAUDOUT
↑
t
BLD
6
55
40
30
25
ns
t
d2
Delay time, XIN
↑↓
to BAUDOUT
↓
t
BHD
6
55
40
30
25
ns
11
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