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參數資料
| 型號： | TL16C2552RHB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS |
| 中文描述： | 1.8 V至5 V雙的UART具有16字節(jié)FIFO |
| 文件頁數： | 31/34頁 |
| 文件大小： | 407K |
| 代理商： | TL16C2552RHB |
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Transmitter Holding Register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is derived from the input clock divided by the programmed devisor. Transmitter section
control is a function of the ACE line control register.
Alternate Function Register (AFR) - Read/Write
This register is used to select specific modes of MF operation and to allow both UART register sets to be written
concurrently.
AFR[0]: Concurrent Write Mode
AFR[2:1]: MF Output Select
AFR[7:3]: Reserved
TL16C2552
SLWS163A–SEPTEMBER 2005–REVISED JUNE 2006
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at TX. In the TL16C450 mode, if the THR is empty and the
transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR bit 7 of both channels are in the same state before executing a concurrent write to the
registers at addresses 0, 1, or 2.
Logic 0 = No concurrent write (default)
Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
These bits select a signal function for output on the MF A/B pins. These signal functions are described as: OP,
BAUDOUT, or RXRDY. Only one signal function can be selected at a time.
MF Function
Bit 2
0
0
1
1
Bit 1
0
1
0
1
MF Function
OP (default)
BAUDOUT
RXRDY
Reserved
All are initialized to logic 0.
Table 12. Typical Package Thermal Resistance Data
Package
32-Pin TQFP RHB
44-Pin PLCC FN
θ
JA
= xx
°
C/W
θ
JA
= 46.2
°
C/W
θ
JC
= xx
°
C/W
θ
JC
= 22
°
C/W
Table 13. Typical Package Weight
Package
Weight in Grams
0.15
0.5
32-Pin TQFP RHB
44-Pin PLCC FN
31
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| TL16C2752FN | 功能描述:UART 接口集成電路 1.8V to 5V Dual UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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| TL16C2752FNR | 功能描述:UART 接口集成電路 1.8V to 5V Dual UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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