參數(shù)資料
型號(hào): TL16C2552RHB
廠商: Texas Instruments, Inc.
英文描述: 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
中文描述: 1.8 V至5 V雙的UART具有16字節(jié)FIFO
文件頁數(shù): 12/34頁
文件大小: 407K
代理商: TL16C2552RHB
www.ti.com
RECEIVER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
TRANSMITTER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MODEM CONTROL SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
TL16C2552
SLWS163A–SEPTEMBER 2005–REVISED JUNE 2006
LIMITS
ALT.
SYMBOL
TEST
PARAMETER
FIGURE
1.8 V
2.5 V
3.3 V
5 V
UNIT
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
d12
Delay time, RCLK to sample
t
SCD
9
20
15
10
10
ns
t
d13
Delay time, stop to set INT or read RBR to LSI
interrupt or stop to RXRDY
t
SINT
8, 9, 10,
11, 12
1
1
1
1
RCLK
cycle
t
d14
Delay time, read RBR/LSR to reset INT
t
RINT
8, 9, 10,
11, 12
C
L
= 30 pF
100
90
80
70
ns
t
d26
Delay time, RCV threshold byte to RTS
19
C
L
= 30 pF
2
baudout
cycles
(2)
t
d27
Delay time, read of last byte in receive FIFO to
RTS
19
C
L
= 30 pF
2
baudout
cycles
t
d28
Delay time, first data bit of 16th character to RTS
20
C
L
= 30 pF
2
baudout
cycles
t
d29
Delay time, RBRRD low to RTS
20
C
L
= 30 pF
2
baudout
cycles
(1)
In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register).
A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.
(2)
LIMITS
TEST
PARAMETER
ALT. SYMBOL
FIGURE
1.8 V
2.5 V
3.3 V
5 V
UNIT
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
d15
Delay time, initial write to transmit start
t
IRS
14
8
24
8
24
8
24
8
24
baudout
cycles
t
d16
Delay time, start to INT
t
STI
14
8
10
8
10
8
10
8
10
baudout
cycles
t
d17
Delay time, IOW (WR THR) to reset INT
t
HR
14
C
L
= 30 pF
70
60
50
50
ns
t
d18
Delay time, initial write to INT (THRE
(1)
)
t
SI
14
16
34
16
34
16
34
16
34
baudout
cycles
t
d19
Delay time, read IOR
to reset INT (THRE
(1)
)
t
IR
14
C
L
= 30 pF
70
50
35
35
ns
t
d20
Delay time, write to TXRDY inactive
t
WXI
15, 16
C
L
= 30 pF
60
45
35
35
ns
t
d21
Delay time, start to TXRDY active
t
SXA
15, 16
C
L
= 30 pF
9
9
9
9
baudout
cycles
t
SU4
Setup time, CTS
before midpoint of stop bit
18
30
20
10
10
ns
t
d25
Delay time, CTS low to TX
18
C
L
= 30 pF
24
24
24
24
baudout
cycles
(1)
THRE = Transmitter Holding Register Empty; IIR = Interrupt Identification Register.
LIMITS
ALT.
SYMBOL
TEST
PARAMETER
FIGURE
1.8 V
2.5 V
3.3 V
5 V
UNIT
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
d22
Delay time, WR MCR to output
t
MDO
17
C
L
= 30 pF
90
70
60
50
ns
t
d23
Delay time, modem interrupt to set INT
t
SIM
17
C
L
= 30 pF
60
50
40
35
ns
t
d24
Delay time, RD MSR to reset INT
t
RIM
17
C
L
= 30 pF
80
60
50
40
ns
12
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