參數(shù)資料
型號： TL16C2552RHB
廠商： Texas Instruments, Inc.
英文描述： 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
中文描述： 1.8 V至5 V雙的UART具有16字節(jié)FIFO
文件頁數(shù)： 23/34頁
文件大?。?/td> 407K
代理商： TL16C2552RHB
www.ti.com
Accessible Registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in
Table 2
. These registers control ACE operations, receive data, and transmit data. Descriptions of
these registers follow
Table 3
.
FIFO Control Register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling.
Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
Bits 4 and 5: These two bits are reserved for future use.
Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see
Table 4
).
TL16C2552
SLWS163A–SEPTEMBER 2005–REVISED JUNE 2006
Table 3. Summary of Accessible Registers
BIT
NO.
REGISTER ADDRESS
DLAB = 0
DLAB = 1
0
0
1
2
2
3
4
5
6
7
0
1
2
Receiver
Buffer
Register
(Read
Only)
Transmitte
r Holding
Register
(Write
Only)
Interrupt
Enable
Register
Interrupt
Ident
.Register
(Read
Only)
FIFO
Control
Register
(Write
Only)
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
Divisor
Latch
(MSB)
Alternate
Function
Register
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
AFR
0
Data Bit
0
(1)
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERBI)
0 if
FIFO
Enable
Word
Length
Select Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta Clear
to Send
(
CTS)
Bit 0
Bit 0
Bit 8
Concurrent
Write
Interrupt
Pending
1
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Interrupt ID
Bit 1
Receiver
FIFO
Reset
Word
Length
Select Bit 1
(WLS1)
Request to
Send
(RTS)
Overrun
Error (OE)
Delta Data
Set Ready
(
DSR)
Bit 1
Bit 1
Bit 9
BAUDOUT
Select
2
Data Bit 2
Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt ID
Bit 2
Transmitter
FIFO
Reset
Number of
Stop Bits
(STB)
OUT1
Parity Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
RXRDY
Select
3
Data Bit 3
Data Bit 3
Enable
Modem
Status
Interrupt
(EDSSI)
Interrupt ID
Bit 3
(2)
DMA Mode
Select
Parity
Enable
(PEN)
INT
Framing
Error (FE)
Delta Data
Carrier
Detect
(
DCD)
Bit 3
Bit 3
Bit 11
0
Enable, OP
Control
4
Data Bit 4
Data Bit 4
0
0
Reserved
Even Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear to
Send
(CTS)
Bit 4
Bit 4
Bit 12
0
5
Data Bit 5
Data Bit 5
0
0
Reserved
Stick Parity
Autoflow
Control
Enable
(AFE)
Transmitter
Holding
Register
(THRE)
Data Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
0
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(2)
Receiver
Trigger
(LSB)
Break
Control
0
Transmitter
Empty
(TEMT)
Ring
Indicator
(RI)
Bit 6
Bit 6
Bit 14
0
7
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(2)
Receiver
Trigger
(MSB)
Divisor
Latch
Access Bit
(DLAB)
0
Error in
RCVR
FIFO
(2)
Data
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
0
(1)
(2)
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
These bits are always 0 in the TL16C450 mode.
23
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