參數(shù)資料
型號(hào)： TL16C2552RHB
廠商： Texas Instruments, Inc.
英文描述： 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
中文描述： 1.8 V至5 V雙的UART具有16字節(jié)FIFO
文件頁(yè)數(shù)： 3/34頁(yè)
文件大小： 407K
代理商： TL16C2552RHB
www.ti.com
TL16C2552 Block Diagram
Crystal
OSC
Buffer
Data Bus
Interface
A2 A0
D7 D0
CS
CHSEL
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
MFA
MFB
RESET
XTAL1
XTAL2
BAUD
Rate
Gen
16 Byte Tx FIFO
16 Byte Rx FIFO
Tx
Rx
UART Channel A
BAUD
Rate
Gen
16 Byte Tx FIFO
16 Byte Rx FIFO
Tx
Rx
UART Channel B
CTSA
DTRA
DSRA, RIA, CDA
RTSA
CTSB
DTRB
DSRB, RIB, CDB
RTSB
V
CC
GND
TXA
RXA
TXB
RXB
UART Regs
UART Regs
DEVICE INFORMATION
TL16C2552
SLWS163A–SEPTEMBER 2005–REVISED JUNE 2006
A.
MF output allows selection of OP, BAUDOUT, or RXRDY per channel.
TERMINAL FUNCTIONS
TERMINAL
FN NO.
10
14
15
I/O
DESCRIPTION
NAME
A0
A1
A2
RHB NO.
3
6
7
I
I
I
Address 0 select bit. Internal registers address selection
Address 1 select bit. Internal registers address selection
Address 2 select bit. Internal registers address selection
Carrier detect (active low). These inputs are associated with individual UART channels A and
B. A low on these pins indicates that a carrier has been detected by the modem for that
channel. The state of these inputs is reflected in the modem status register (MSR).
Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0.
A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A.
CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate
function register (AFR) can temporarily override CHSEL function, allowing the user to write to
both channel register simultaneously with one write cycle when CS is low. It is especially
useful during the initialization routine.
UART chip select (active low). This pin selects channel A or B in accordance with the state of
the CHSEL pin. This allows data to be transferred between the user CPU and the 2552.
Clear to send (active low). These inputs are associated with individual UART channels A and
B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit
data from the 2552. Status can be tested by reading MSR bit 4. These pins only affect the
transmit and receive operations when auto CTS function is enabled through the enhanced
feature register (EFR) bit 7, for hardware flow control operation.
CDA, CDB
42, 30
–
I
CHSEL
16
8
I
CS
18
10
I
CTSA,
CTSB
40, 28
25, 17
I
3
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