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Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
18
L Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order
(continued)
Table 2 shows the list of the TFRA08C13 pins and a functional description for each.
Table 2. Pin Descriptions
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
DS1/CEPT3
A2
A6
A9
SECOND
MPCLK
RCHIDATAB4
TFDLCK4
TFS4
AD1
AD5
AD7
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
AF2
RFDLCK4
RFRMDATA4
NC
TND4
V
SS
TPD5
NC
NC
NC
TLCK5
NC
RFRMCLK3
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
V
DD
RLCK3
V
DD
A5
A7
A11
MPMODE
RPD4
TFDL4
TCRCMFS4
TCHIDATA4
AD3
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AD6
NC
RSSFS4
NC
TLCK4
RLCK4
RLCK5
TND5
NC
NC
NC
NC
Pins
Symbol
Type
*
Description
AF3, AF5,
AD18, K25,
E24, K4,
M2, U3
AD20, AD26,
AE21, G3,
K24,
A18, J3, C7,
Y2
D17
V
DD
P
3.3 V Power Supply.
3.3 V ± 5%. Each of these pins must be bypassed
with a 0.1
μ
F capacitor to V
SS
, as close to the pin as possible.
V
SS
G
Ground.
V
DDA
P
3.3 V Quiet Analog Power Supply.
This pin must be bypassed with a
0.1
μ
F capacitor to V
SSA
, as close to the pin as possible. In addition,
this pin should be isolated from the 3.3 V power plane with an inductive
bead.
3.3 V Quiet Analog Ground.
3.3 V Quiet Digital Power Supply.
This pin must be bypassed with a
0.1
μ
F capacitor to V
SSD
, as close to the pin as possible. In addition,
this pin should be isolated from the 3.3 V power plane with an inductive
bead.
3.3 V Quiet Digital Ground.
3-State (Active-Low).
Asserting this pin low forces the channel outputs
into a high-impedance state.
Reset (Active-Low).
Asserting this pin low resets all channels on the
entire device.
C17
A14
V
SSA
V
DDD
G
P
A13
B18
V
SSD
3-STATE
G
I
u
C19
RESET
I
u
* I
u
indicates an internal pull-up, I
d
indicates an internal pull-down.
After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
Asserting this pin low will initially force RDY to a low state.