參數(shù)資料
型號: TDA9105
廠商: 意法半導(dǎo)體
英文描述: Deflection Processor for Multisync Monitors(偏轉(zhuǎn)處理器)
中文描述: 偏轉(zhuǎn)處理器的多頻顯示器(偏轉(zhuǎn)處理器)
文件頁數(shù): 6/32頁
文件大?。?/td> 339K
代理商: TDA9105
HORIZONTAL SECTION
(continued)
ElectricalCharacteristics
(V
CC
= 12V,T
amb
= 25
°
C)
Symbol
SUPPLY AND REFERENCE VOLTAGES
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
I
CC
V
REF-H
I
REF-H
V
REF-V
I
REF-V
INPUT SECTION/PLL1
Supply Voltage (Pin 18)
Supply Current (Pin 18)
Reference Voltage for Horizontal Section (Pin 7)
Max Sourced Current on V
REF-H
(Pin 7)
Reference Voltage for Vertical Section (Pin 26)
Max Sourced Current on V
REF-V
(Pin 26)
10.8
12
40
8
13.2
60
8.6
5
8.6
5
V
See Figure 1
I = 2mA
mA
V
mA
V
mA
7.4
I = 2mA
7.4
8
V
INTH
Horizontal Input Threshold Voltage (Pin 17)
Low level voltage
High level voltage
V
REF-H
= 8V
R0 = 6.49k
, C0 = 680pF
% of Horizontalperiod
R0 = 6.49k
, C0 = 680pF
R0 = 6.49k
, C0 = 680pF
See conditions on Fig. 1
2
0.8
V
V
VCO
V
COG
Hph
f0
CR
VCO Control Voltage (Pin 12)
VCO Gain, dF/dV (Pin 12)
Horizontal Phase Adjust(Pin 15)
FreeRunning Frequency (adjustable by changing R0)
PLL1 Capture Range
1.6 to 6.2
17
±
12.5
27
V
kHz/V
%
kHz
25
29
Fh Min
Fh Max
PLL ON
PLL OFF
f0
3.7 x f0
kHz
kHz
V
V
mA
V
PLLinh
PLL 1 Inhibition (Pin 14)
(Typ. Threshold = 1.6V)
Max Output Current on HLock Output
Low Level Voltage on HLock Output
V
14
V
14
I
2
V
2
with I
2
= 10mA
2
0.8
I
HLock0
V
HLock0
SECOND PLL AND HORIZONTAL OUTPUT SECTION
10
0.5
0.25
FBth
Hjit
Flyback Input Threshold Voltage (Pin 5)
Horizontal Jitter
See Figure 14
See Application Diagram
(Pins8-9)
0.65
0.75
80
V
ppm
HDmin
HDmax
HDvd
Horizontal Drive OutputDuty-cycle
(Pin 20 or 21) (see Note)
Minimum
Maximum
Horizontal Drive Low Level Output Voltage
V
4
= 2V
V
4
= 6V
V
4
= V
REF
- 100mV
Pin 20 to GND,
V
21
-V
20
, I
OUT
= 20mA
Pin 21 to V
CC
,
I
OUT
= 20mA
32
53.5
57.5
34
56
60
1.1
36
58.5
62.5
1.7
%
%
%
V
HDem
Horizontal Drive High Level Output Voltage
(output on Pin 20)
X-RAY Protection Input Threshold Voltage (Pin 16)
Maximum Output Current on Composite
Blanking Output
Low-Level Voltage on Composite Blanking
Output (Blanking ON)
Maximum Output Current on Moire Output
VSmoiO Low-Level Voltage on Moire Output
Vphi2
Internal Clamping Voltage on 2nd PLL Loop
Filter Output (Pin3)
V
OFF
Threshold Voltage to Stop H-out, V-out and to
Activate BLKout (OFF Mode when V
4
< V
OFF
)
(Pin 4)
VSCinh
Supply Voltage to Stop H-out, V-out when
V
CC
< VSCinh (Pin18)
9.5
10
V
XRAYth
ISblkO
TBD
8
TBD
10
V
I
22
mA
VSblkO
V
22
with I
22
= 10mA
0.25
0.5
V
ISmoiO
I
23
V
23
with I
23
= 10mA
Vmin
Vmax
V
4
10
0.5
mA
V
V
V
V
0.25
1.6
3.2
1
TBD
7.5
V
Note :
IfH-drive is taken on Pin 20 (Pin 21 connected to supply),H-D is the ratio of low level duration to horizontal period.
IfH-drive is taken on Pin 21 (Pin 20 grounded), H-D is the ratio of high level duration to horizontal period.
In both cases, H-D period driving horizontal scanning transistor off.
9
TDA9105
6/32
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