參數(shù)資料
型號: TDA9105
廠商: 意法半導(dǎo)體
英文描述: Deflection Processor for Multisync Monitors(偏轉(zhuǎn)處理器)
中文描述: 偏轉(zhuǎn)處理器的多頻顯示器(偏轉(zhuǎn)處理器)
文件頁數(shù): 19/32頁
文件大?。?/td> 339K
代理商: TDA9105
OPERATINGDESCRIPTION
(continued)
Moire Function
Figure 18 :
Moire Function BlockDiagram
23
Ck
D
Q
Q
Rst
H-SYNC
Ck
D
Q
Q
Monostable
V-SYNC
9
H
V
MOIRE
H
V
MOIRE
ODD FRAME
EVEN FRAME
9
Figure 19 :
Moire Output Waveform
Geometric Corrections
The principle is represented in Figure20.
Starting from the vertical ramp, a parabolashaped
is generatedforE/Wcorrection,dynamichorizontal
phase control correction, and vertical dynamicFo-
cus correction.
The core of the parabola generator is an analog
multiplier. The output current of which is equal to :
I = k (V
RAMP
- V
DCIN)2
.
Where V
RAMP
is the vertical ramp, typically com-
prised between 2 and 5V, V
DCIN
is a vertical DC
input adjustablein the range 3.2V
3.8Vin order
to generate a dissymmetric parabola if required
(keystoneadjustment).
In orderto keepgoodscreen geometryforany end
user preferencesadjustment we implemented the
possibilityto have ”
geometrytracking
”.To enable
the ”tracking” function, the V
DCOUT
must be con-
nected to V
DCIN
.
It is possible to inhibit V
POS
tracking by applying a
fixed DC voltageon theV
DCIN
Pin.
This DC voltage in that case must be taken from
the verticalreference and adjustedto 3.5V with an
externalbridge resistor.
Due to large output stages voltage range (E/W,
BALANCE, FOCUS), the combination of tracking
function with maximum vertical amplitude max. or
min.vertical position and maximum gainontheDC
control inputs mayleads to the outputstages satu-
ration. This must be avoided by limiting the output
voltageby apropriateDC controlvoltages.
TDA9105
19/32
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