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參數(shù)資料
| 型號： | TDA9105 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Deflection Processor for Multisync Monitors(偏轉(zhuǎn)處理器) |
| 中文描述： | 偏轉(zhuǎn)處理器的多頻顯示器（偏轉(zhuǎn)處理器） |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 339K |
| 代理商： | TDA9105 |
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OPERATINGDESCRIPTION
(continued)
Figure 8 :
Principle Diagram
LOCKDET
2
H-LOCKOUT
13
H-LOCKCAP
COMP1
INPUT
INTERFACE
17
H-SYNC
High
CHARGE
PUMP
Low
PLL
INHIBITION
VCO
14
PLL1INHIB
12
11
10
PLL1F
R0
C0
PHASE
ADJUST
E2
15
H-POS
3.2V
OSC
9
The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
charge pump. A”CRC”filter is generally used(see
Figure 9).
PLL1 is inhibited by applying a high level on Pin 14
(PLLinhib)whichisaTTLcompatibleinput.Theinhibi-
tion results from the openingof a switch located be-
tweenthechargepumpandthefilter (see Figure8).
The VCOuses an externalRC network. It delivers
a linear sawtooth obtained by charge and dis-
charge of the capacitor, bya current proportionnal
to the current in the resistor. typical thresholds of
sawtooth are 1.6Vand 6.4V (see Figure 10).
The control voltage of the VCO is typically com-
prised between 1.6V and 6V (see Figure 10). The
theoreticalfrequencyrangeofthis VCOisintheratio
1
→
3.75, but due to spread and thermal drift of
externalcomponentsandthecircuititself,theeffec-
12
PLL1F
9
Figure 9
tive frequencyrange has to be smaller (e.g.30kHz
→
85kHz).In theabsenceofsynchronisationsignal
thecontrolvoltageisequalto1.6Vtyp.andtheVCO
oscillates on its lowest frequency(free frequency).
Thesynchrofrequencyhastobealwayshigherthan
thefreefrequencyanda marginhastobe taken.As
an example for a synchro range from 30kHz to
85kHz, thesuggestedfree frequencyis 27kHz.
11
12
Loop
Filter
R0
1.6V
6.4V
10
C0
6.4V
1.6V
0
0.75T T
RS
FLIPFLOP
(1.6V < V
< 6V)
12
I
0
I
0
2
4 I
0
2
9
Figure 10 :
Detailsof VCO
TDA9105
15/32
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