- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372453 > TDA9105 (意法半導(dǎo)體) Deflection Processor for Multisync Monitors(偏轉(zhuǎn)處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | TDA9105 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Deflection Processor for Multisync Monitors(偏轉(zhuǎn)處理器) |
| 中文描述： | 偏轉(zhuǎn)處理器的多頻顯示器（偏轉(zhuǎn)處理器） |
| 文件頁(yè)數(shù)： | 16/32頁(yè) |
| 文件大?。?/td> | 339K |
| 代理商： | TDA9105 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)當(dāng)前第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)
OPERATINGDESCRIPTION
(continued)
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
adjustablebetween 2.4Vand 4V (byPin 15). So a
±
45
°
phaseadjustment is possible (see Figure 11).
20k
220nF
13
From
Phase
Comparator
NOR1
A
6.5V
B
H-Lock CAP
2
HLOCKOUT
9
Figure 12 :
LOCK/UNLOCK Block Diagram
H Osc
Sawtooth
Phase REF1
H Synchro
1.6V
Vb
6.4V
2.4V<Vb<4V
0.75T
0.25T
Phase REF1 isobtainedby comparisonbetween the sawtoothand
a DCvoltage adjustable between 2.4V and 4V. The PLL1 ensures
the exact
coincidence between the signals phase REF and
HSYNS.A
±
T/8 phase adjustment is possible.
9
Figure11 :
PLL1 Timing Diagram
The twoVCO thresholdcan be filteredby connect-
ing capacitoron Pins8-9.
The TDA9103 also includes a LOCK/UNLOCK
identification block which senses in real-time
whetherthePLLis lockedon the incominghorizon-
tal sync signal or not. The resulting information is
available on HLOCKOUToutput (Pin 2).The block
diagram of the LOCK/UNLOCK function is de-
scribed in Figure 12.
The NOR1 gateis receivingthe phasecomparator
output pulses (which alsodrive the chargepump).
When the PLLis locked, on point
A
thereis a very
small negative pulse (100ns) at each horizontal
cycle, so after R-C filter, there is a high level on
Pin13 which force HLOCKOUT to high level (pro-
videdthat HLOCKOUT is pulled up to V
CC
).
When the PLL is unlocked, the 100ns negative
pulseon
A
becomesmuchlargerandconsequently
the average level on Pin13 willdecrease. When it
reaches 6.5V, point
B
goes to low level forcing
HLOCKOUT output to ”0”.
The statusof Pin13 isapproximatelythefollowing :
- Near 0V when there is no H-SYNC,
- Between0and4V withH-SYNCfrequencydiffer-
ent from VCO,
- Between 4 and 8V when H-SYNC frequency
= VCOfrequency but not in phase,
- Near to 8V when PLLis locked.
It is important to notice thatPin 13 is not anoutput
pinandmust onlybeusedforfilteringpurpose(see
Figure 12).
TDA9105
16/32
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA9106A | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9106 | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDE1737 | Interface Circuit - Relay and Lamp-Driver(接口電路(單片放大器驅(qū)動(dòng)繼電器和電子管)) |
| TDE1779ASP | DUAL 2-A SOURCE DRIVER |
| TDF1779 | DUAL 2-A SOURCE DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9105A | 制造商:Panasonic Industrial Company 功能描述:IC |
| TDA9106 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9106A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9108 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MONITOR HORIZONTAL PROCESSOR |
| TDA9109 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。