參數(shù)資料
型號(hào): TC9324F
廠商: Toshiba Corporation
英文描述: Single-Chip DTS Microcontroller (DTS-20)
中文描述: 單芯片微丘(丘- 20)
文件頁數(shù): 76/101頁
文件大?。?/td> 1831K
代理商: TC9324F
TC9324F
2002-02-08
76
10) BUSY Bit
The BUSY bit is used to reference the serial operation state.
When a serial operation starts (when the STA bit is set to 1 or the serial operation start conditions
are satisfied), BUSY is set to 1. Before attempting to reference serial data, first check that this bit is
set to 0.
The falling edge of the BUSY bit generates interrupt requests (on completion of a serial operation).
11) COUNT Bit
The COUNT bit is used to determine whether data have been sent or received in 4-bit units.
When the number of shift operations is a multiple of 4, the COUNT bit outputs 0. When not a
multiple of 4, the bit outputs 1. COUNT is reset to 0 whenever the F/F reset bit is set to 1.
12) SIO F/F Bit
The SIO F/F bit is set to 1 when the SCK3/SCK4 pin starts a clock operation. When TC9324F is set
as a master (serial clock set to external input), this bit can be used to check whether a serial operation
has started or is suspended. The SIO F/F bit is reset to 0 whenever the F/F reset bit is set to 1.
13) SO-NG F/F Bit
When serial data are output, this bit can be used to check whether the correct data have been
output. When the Nch bit is set to 1 (N-channel open drain output), the SO-NG F/F bit is valid.
When the SO-NG F/F bit is set to 0, the data output is normal; when the bit is set to 1, the data
output is abnormal.
When the data output is confirmed as abnormal with 2-line serial interface set, the ENA, SO3/SO4,
and SCK3/SCK4 bits are all set to 1, the serial clock and serial data pins are open, and high
impedance is set. This overrides the master restrictions when multiple masters are set and
simultaneously outputting data. After this, serial operations continue until the completion of 8-bit
data serial operations. Then, after checking that the serial operations have completed (BUSY3), the
serial data can be referenced.
Even though the data output is judged abnormal with 3-line serial interface set, no setting of the
ENA, SO3/SO4, and SCK3/SCK4 bits takes place and their status is unchanged. In this case, the
SO-NG F/F bit is used to determine whether the data output is normal or abnormal.
The SO-GN F/F bit is reset to 0 whenever the F/F reset bit is set to 1.
14) STA Bit
This bit is used to start serial interface operations.
When 3-line serial interface is set, each setting of the STA bit to 1 starts a serial operation.
Setting STA to 1 transfers serial output data to the shift register. When the serial clock is set to an
internal clock (master), a serial clock is output. When the serial clock is set to an external clock
(slave), the interface stands by for serial clock input.
When 2-line serial interface is set, inputting the start conditions to the SCK4 and SO4 pins
automatically starts serial operations. When TC9324F is set as the master, a serial clock (SCK4) is
output for serial operations. When TC9324F is a slave, an external serial clock is used for serial
operations. When receiving or sending data equal to or larger than two bytes, setting STA to 1 on
completion of serial operations on the first byte transfers the serial output data to the shift register
and starts serial operations on the falling edge of the next serial clock.
tmax
=
When 4.5-MHz CPU clock used: 1.11
μ
s
When 75-kHz CPU clock used: 13.3
μ
s
SCK3/SCK4 pin
Maximum tmax
Serial clock output
Serial clock output restarted
Wait released
Wait period
Forcible wait set by external device
(External device outputs L level)
ENA bit
SO3/SO4 pin
SO-NG F/F bit
SCK3/SCK4 pin
When 2-line serial interface is set, the ENA bit is set to
1 and the serial clock data pin is open.
L level output by other external device
TC9324F serial output
(In 2-line serial interface this output pin is open.)
Serial data abnormal
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