參數(shù)資料
型號(hào)： TC9324F
廠商： Toshiba Corporation
英文描述： Single-Chip DTS Microcontroller (DTS-20)
中文描述： 單芯片微丘（丘- 20）
文件頁(yè)數(shù)： 38/101頁(yè)
文件大?。?/td> 1831K
代理商： TC9324F
TC9324F
2002-02-08
38
When using multiple interrupts, note the following.
1)
2)
3)
Priority of interrupt sources
Restrictions on the address stack levels used when an interrupt request is issued
Saving the carry flag and data memory
(1)
Priority of interrupt sources
The priority of multiple interrupts is: A
<
B
<
C
<
D as shown in the diagram. Under this priority, a
C interrupt must be given preference even though interrupt A or B is being processed. And a D
interrupt must be given priority even though a C interrupt is being processed.
A priority for handling multiple interrupts must be determined because of the following
hypothetical situation. There are two interrupt sources, A and B. Source A issues a request every 10
ms and the time for handling interrupt A is 4 ms. While source B issues a request every 2 ms and the
time for handling interrupt B is 1 ms. If no priority were established for A and B, while interrupt B
was being processed, interrupt A would be accepted and processed as a result of an interrupt A
request, and interrupt B processing would be repeatedly held up. To prevent this situation, set a
priority (A
<
B) to disable other interrupts during processing of interrupt B and write a program to
allow interrupt B to be accepted even during processing of interrupt A.
When all the individual enable flags are set to 1 (interrupts enabled), the priority is determined by
the hardware described in the interrupt priority circuit block section. However, by manipulating the
individual enable flags by software, the hardware priority can be changed. Normally, in the interrupt
handling routine, accepted interrupts and low-priority interrupts are disabled and high-priority
interrupts are enabled.
(2)
Restrictions on address stack levels
When an interrupt request is issued, the return address is automatically saved to the address stack,
as described in the section on interrupt acceptance procedure. The address stack consists of 16 levels,
as mentioned in the stack register section, and the address stack can be used even while subroutine
call instructions are being executed. Therefore, take care not to exceed the 16 interrupt and
subroutine call levels. If these exceed 16, the recorded return addresses are corrupted from the first
stack.
(3)
Saving
When using multiple interrupts, be sure to secure separate saving areas for each interrupt source.
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