參數(shù)資料
型號: T89C51CC01UA-SLSIM
廠商: Atmel
文件頁數(shù): 9/123頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K 44PLCC
標準包裝: 27
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC01UASLSIM
PIC18F2XK20/4XK20
DS41303G-page 106
2010 Microchip Technology Inc.
Example 8-3 shows the sequence to do a 16 x 16
unsigned
multiplication.
shows
the
algorithm that is used. The 32-bit result is stored in four
registers (RES<3:0>).
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES<3:0>). To account for the sign bits of the argu-
ments, the MSb for each argument pair is tested and
the appropriate subtractions are done.
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
RES3:RES0
=
ARG1H:ARG1L
ARG2H:ARG2L
=
(ARG1H
ARG2H 216) +
(ARG1H
ARG2L 28) +
(ARG1L
ARG2H 28) +
(ARG1L
ARG2L)
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
MOVFF
PRODH, RES1
;
MOVFF
PRODL, RES0
;
MOVF
ARG1H, W
MULWF
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
MOVFF
PRODH, RES3
;
MOVFF
PRODL, RES2
;
MOVF
ARG1L, W
MULWF
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1, F
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2, F
;
CLRF
WREG
;
ADDWFC
RES3, F
;
MOVF
ARG1H, W
;
MULWF
ARG2L
; ARG1H * ARG2L->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1, F
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2, F
;
CLRF
WREG
;
ADDWFC
RES3, F
;
RES3:RES0 = ARG1H:ARG1L
ARG2H:ARG2L
= (ARG1H
ARG2H 216) +
(ARG1H
ARG2L 28) +
(ARG1L
ARG2H 28) +
(ARG1L
ARG2L) +
(-1
ARG2H<7> ARG1H:ARG1L 216) +
(-1
ARG1H<7> ARG2H:ARG2L 216)
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF
PRODH, RES1
;
MOVFF
PRODL, RES0
;
MOVF
ARG1H, W
MULWF
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF
PRODH, RES3
;
MOVFF
PRODL, RES2
;
MOVF
ARG1L, W
MULWF
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1, F
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2, F
;
CLRF
WREG
;
ADDWFC
RES3, F
;
MOVF
ARG1H, W
;
MULWF
ARG2L
; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1, F
; Add cross
MOVF
PRODH, W
; products
ADDWFC
RES2, F
;
CLRF
WREG
;
ADDWFC
RES3, F
;
BTFSS
ARG2H, 7
; ARG2H:ARG2L neg?
BRA
SIGN_ARG1
; no, check ARG1
MOVF
ARG1L, W
;
SUBWF
RES2
;
MOVF
ARG1H, W
;
SUBWFB
RES3
;
SIGN_ARG1
BTFSS
ARG1H, 7
; ARG1H:ARG1L neg?
BRA
CONT_CODE
; no, done
MOVF
ARG2L, W
;
SUBWF
RES2
;
MOVF
ARG2H, W
;
SUBWFB
RES3
;
CONT_CODE
:
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