參數(shù)資料
型號: T89C51CC01UA-SLSIM
廠商: Atmel
文件頁數(shù): 85/123頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K 44PLCC
標準包裝: 27
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC01UASLSIM
24
A/T89C51CC01
4129N–CAN–03/08
Internal Space
Lower 128 Bytes RAM
The lower 128 Bytes of RAM (see Figure 11) are accessible from address 00h to 7Fh
using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4
banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 18)
select which bank is in use according to Table 16. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct address-
ing, and can be used for context switching in interrupt service routines.
Table 16. Register Bank Selection
The next 16 Bytes above the register banks form a block of bit-addressable memory
space. The C51 instruction set includes a wide selection of single-bit instructions, and
the 128 bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00h to 7Fh.
Figure 12. Lower 128 Bytes Internal RAM Organization
Upper 128 Bytes RAM
The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
addressing mode.
Expanded RAM
The on-chip 1024 Bytes of expanded RAM (XRAM) are accessible from address 0000h
to 03FFh using indirect addressing mode through MOVX instructions. In this address
range, the bit EXTRAM in AUXR register is used to select the XRAM (default) or the
XRAM. As shown in Figure 11 when EXTRAM = 0, the XRAM is selected and when
EXTRAM = 1, the XRAM is selected.
The size of XRAM can be configured by XRS1-0 bit in AUXR register (default size is
1024 Bytes).
Note:
Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile
memory cells. This means that the RAM content is indeterminate after power-up and
must then be initialized properly.
RS1
RS0
Description
0
Register bank 0 from 00h to 07h
0
1
Register bank 0 from 08h to 0Fh
1
0
Register bank 0 from 10h to 17h
1
Register bank 0 from 18h to 1Fh
Bit-Addressable Space
4 Banks of
8 Registers
R0-R7
30h
7Fh
(Bit Addresses 0-7Fh)
20h
2Fh
18h
1Fh
10h
17h
08h
0Fh
00h
07h
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