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| 型號(hào)： | T89C51CC01UA-SLSIM |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 45/123頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU FLASH 32K 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | AT89C CAN |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | CAN，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 1.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 配用： | AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN |
| 其它名稱(chēng)： | T89C51CC01UASLSIM |
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2007 Microchip Technology Inc.
Preliminary
DS70165E-page 137
dsPIC33F
write collision (PWCOLx) status bits in a DMAC Status
register (DMACS0) to allow the DMAC error trap
handler to determine the source of the Fault condition.
7.2.1
BYTE OR WORD TRANSFER
Each DMA channel can be configured to transfer
words or bytes. As usual, words can only be moved to
and from aligned (even) addresses. Bytes can be
moved to or from any (legal) address.
If the SIZE bit (DMAxCON<14>) is clear, word sized
data is transferred. The LSb of the DMA RAM Address
register (DMAxSTA or DMAxSTB) is ignored. If
Post-Increment Addressing mode is enabled, the DMA
RAM Address register is incremented by 2 after every
word transfer.
If the SIZE bit is set, byte sized data is transferred. If
Post-Increment Addressing is enabled, the DMA RAM
Address register is incremented by 1 after every byte
transfer.
7.2.2
ADDRESSING MODES
The DMAC supports Register Indirect and Register
Indirect Post-Increment Addressing modes for DMA
RAM addresses (source or destination). Each channel
can select the DMA RAM Addressing mode indepen-
dently. The Peripheral SFR is always accessed using
Register Indirect Addressing.
If the AMODE<1:0> bits (DMAxCON<5:4>) are set to
‘01’,
Register
Indirect
Addressing
without
Post-Increment is used, which implies that the DMA
RAM address remains constant.
If the AMODE<1:0> bits are clear, DMA RAM is
accessed using Register Indirect Addressing with
Post-Increment, which means the DMA RAM address
will be incremented after every access
Any DMA channel can be configured to operate in
Peripheral Indirect Addressing mode by setting the
AMODE<1:0> bits to ‘10’. In this mode, the DMA RAM
source or destination address is partially derived from
the peripheral as well as the DMA Address registers.
Each peripheral module has a pre-assigned peripheral
indirect address which is logically ORed with the DMA
Start Address register to obtain the effective DMA RAM
address. The DMA RAM Start Address register value
must be aligned to a power-of-two boundary.
7.2.3
DMA TRANSFER DIRECTION
Each DMA channel can be configured to transfer data
from a peripheral to DMA RAM, or from DMA RAM to a
peripheral.
If the DIR bit (DMAxCON<13>) is clear, the reads
occur from a peripheral SFR (using the DMA Periph-
eral Address register, DMAxPAD) and the writes are
directed to the DMA RAM (using the DMA RAM
Address register).
If the DIR bit (DMAxCON<13>) is set, the reads occur
from the DMA RAM (using the DMA RAM Address
register) and the writes are directed to the peripheral
(using
the
DMA
Peripheral
Address
register,
DMAxPAD).
7.2.4
NULL DATA PERIPHERAL WRITE
MODE
If the NULLW bit (DMAxCON<11>) is set, a null data
write to the peripheral SFR is performed in addition to
a data transfer from the peripheral SFR to DMA RAM
(assuming the DIR bit is clear). This mode is most use-
ful in applications in which sequential reception of data
is required without any data transmission
Note:
DMAxCNT value is independent of data
transfer size (byte/word). If an address off-
set is required, a 1-bit left shift of the
counter is required to generate the correct
offset for (aligned) word transfers.
Note:
Only the ECAN and ADC modules can use
Peripheral Indirect Addressing
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