參數(shù)資料
型號： T89C51CC01UA-SLSIM
廠商： Atmel
文件頁數(shù)： 12/123頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 32K 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： AT89C CAN
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： CAN，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
配用： AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱： T89C51CC01UASLSIM
2010 Microchip Technology Inc.
DS41303G-page 109
PIC18F2XK20/4XK20
9.4
INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
REGISTER 9-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1
= Enables all unmasked interrupts
0
= Disables all interrupts including peripherals
When IPEN = 1:
1
= Enables all high priority interrupts
0
= Disables all interrupts including low priority.
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1
= Enables all unmasked peripheral interrupts
0
= Disables all peripheral interrupts
When IPEN = 1:
1
= Enables all low priority interrupts
0
= Disables all low priority interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1
= Enables the TMR0 overflow interrupt
0
= Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1
= Enables the INT0 external interrupt
0
= Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit(2)
1
= Enables the RB port change interrupt
0
= Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1
= TMR0 register has overflowed (must be cleared by software)
0
= TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1
= The INT0 external interrupt occurred (must be cleared by software)
0
= The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit(1)
1
= At least one of the RB<7:4> pins changed state (must be cleared by software)
0
= None of the RB<7:4> pins have changed state
Note
1:
A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
2:
RB port change interrupts also require the individual pin IOCB enables.
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