參數(shù)資料
型號(hào)： T89C51CC01UA-SLSIM
廠商： Atmel
文件頁數(shù)： 41/123頁
文件大小： 0K
描述： IC 8051 MCU FLASH 32K 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： AT89C CAN
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： CAN，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 2K x 8
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
配用： AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱： T89C51CC01UASLSIM
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 133
dsPIC33F
6.4
Interrupt Setup Procedures
6.4.1
INITIALIZATION
To configure an interrupt source:
1.
Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
2.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
3.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
4.
Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
6.4.2
INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize
the IVT with the correct vector address will depend on
the programming language (i.e., C or assembler) and
the language development toolsuite that is used to
develop the application. In general, the user must clear
the interrupt flag in the appropriate IFSx register for the
source of interrupt that the ISR handles. Otherwise, the
ISR will be re-entered immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.
6.4.3
TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
6.4.4
INTERRUPT DISABLE
All user interrupts can be disabled using the following
procedure:
1.
Push the current SR value onto the software
stack using the PUSH instruction.
2.
Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POP instruction may be
used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (level 8-level 15)
cannot be disabled.
The DISI instruction provides a convenient way to dis-
able interrupts of priority levels 1-6 for a fixed period of
time. Level 7 interrupt sources are not disabled by the
DISI
instruction.
Note:
At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to priority level 4.
相關(guān)PDF資料
PDF描述
T89C51CC01UA-RLTIM IC 8051 MCU FLASH 32K 44VQFP
T89C51CC01CA-SLSIM IC 8051 MCU FLASH 32K 44PLCC
T89C51CC01CA-RLTIM IC 8051 MCU FLASH 32K 44VQFP
AT91M55800A-33CI IC ARM MCU 33MHZ 176-BGA
10FMN-BMTR-A-TB CONN FMN HSNG 10POS SGL REV SMD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T89C51CC02 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash
T89C51CC02_03 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:CAN Microcontrollers
T89C51CC02_0305 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory
T89C51CC02_0312 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:CAN Microcontrollers
T89C51CC02_06 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*