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參數(shù)資料
| 型號： | T89C51CC01UA-SLSIM |
| 廠商： | Atmel |
| 文件頁數(shù)： | 44/123頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU FLASH 32K 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | AT89C CAN |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | CAN，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 1.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 配用： | AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN |
| 其它名稱： | T89C51CC01UASLSIM |
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dsPIC33F
DS70165E-page 136
Preliminary
2007 Microchip Technology Inc.
FIGURE 7-1:
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
7.1
DMAC Registers
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
A 16-bit DMA Channel Control register
(DMAxCON)
A 16-bit DMA Channel IRQ Select register
(DMAxREQ)
A 16-bit DMA RAM Primary Start Address register
(DMAxSTA)
A 16-bit DMA RAM Secondary Start Address
register (DMAxSTB)
A 16-bit DMA Peripheral Address register
(DMAxPAD)
A 10-bit DMA Transfer Count register (DMAx-
CNT)
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
DMACS0 contains the DMA RAM and SFR write colli-
sion flags, XWCOLx and PWCOLx, respectively.
DMACS1 indicates DMA channel and Ping-Pong
mode status.
The
DMAxCON,
DMAxREQ,
DMAxPAD
and
DMAxCNT are all conventional read/write registers.
Reads of DMAxSTA or DMAxSTB will read the con-
tents of the DMA RAM Address register. Writes to
DMAxSTA or DMAxSTB write to the registers. This
allows the user to determine the DMA buffer pointer
value (address) at any time.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the cor-
responding interrupt priority control bits (DMAxIP) are
located in an IPCx register in the interrupt controller.
7.2
DMAC Operating Modes
Each DMA channel has its own status and control reg-
ister (DMAxCON) that is used to configure the channel
to support the following operating modes:
Word or byte size data transfers
Peripheral to DMA RAM or DMA RAM to
peripheral transfers
Post-increment or static DMA RAM address
One-shot or continuous block transfers
Auto-switch between two start addresses after
each transfer complete (Ping-Pong mode)
Force a single DMA transfer (Manual mode)
Each DMA channel can be independently configured
to:
Select from one of 20 DMA request sources
Manually enable or disable the DMA channel
Interrupt the CPU when the transfer is half or fully
complete
DMA channel interrupts are routed to the interrupt con-
troller module and enabled through associated enable
flags.
The channel DMA RAM and peripheral write collision
Faults are combined into a single DMAC error trap
(Level 10) and are not maskable. Each channel has
DMA RAM write collision (XWCOLx) and peripheral
CPU
SRAM
DMA RAM
CPU Peripheral DS Bus
Peripheral 3
DMA
Peripheral
Non-DMA
SRAM X-Bus
PORT 2
PORT 1
Peripheral 1
DMA
Ready
Peripheral 2
DMA
Ready
DMA DS Bus
CPU
DMA
CPU
DMA
CPU
DMA
Peripheral Indirect Address
Note: CPU and DMA address buses are not shown for clarity.
DMA
Cont
ro
l
DMA Controller
DMA
Channels
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