- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3856 > T89C51CC01UA-SLSIM (Atmel)IC 8051 MCU FLASH 32K 44PLCC PDF資料下載
參數(shù)資料
| 型號： | T89C51CC01UA-SLSIM |
| 廠商： | Atmel |
| 文件頁數(shù)： | 4/123頁 |
| 文件大小： | 0K |
| 描述： | IC 8051 MCU FLASH 32K 44PLCC |
| 標準包裝： | 27 |
| 系列： | AT89C CAN |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | CAN，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 1.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 配用： | AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN |
| 其它名稱： | T89C51CC01UASLSIM |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁
2010 Microchip Technology Inc.
DS41303G-page 101
PIC18F2XK20/4XK20
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write
the address to the EEADR register, clear the EEPGD
control bit of the EECON1 register and then set control
bit, RD. The data is available on the very next instruc-
tion cycle; therefore, the EEDATA register can be read
by the next instruction. EEDATA will hold this value until
another read operation, or until it is written to by the
user (during a write operation).
The basic process is shown in Example 7-1.
7.4
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by
hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared by hardware and the EEPROM Interrupt Flag
bit, EEIF, is set. The user may either enable this
interrupt or poll this bit. EEIF must be cleared by
software.
7.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
EXAMPLE 7-1:
DATA EEPROM READ
EXAMPLE 7-2:
DATA EEPROM WRITE
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
; Data Memory Address to read
BCF
EECON1, EEPGD
; Point to DATA memory
BCF
EECON1, CFGS
; Access EEPROM
BSF
EECON1, RD
; EEPROM Read
MOVF
EEDATA, W
; W = EEDATA
MOVLW
DATA_EE_ADDR_LOW
;
MOVWF
EEADR
; Data Memory Address to write
MOVLW
DATA_EE_ADDR_HI
;
MOVWF
EEADRH
;
MOVLW
DATA_EE_DATA
;
MOVWF
EEDATA
; Data Memory Value to write
BCF
EECON1, EEPGD
; Point to DATA memory
BCF
EECON1, CFGS
; Access EEPROM
BSF
EECON1, WREN
; Enable writes
BCF
INTCON, GIE
; Disable Interrupts
MOVLW
55h
;
Required
MOVWF
EECON2
; Write 55h
Sequence
MOVLW
0AAh
;
MOVWF
EECON2
; Write 0AAh
BSF
EECON1, WR
; Set WR bit to begin write
BSF
INTCON, GIE
; Enable Interrupts
; User code execution
BCF
EECON1, WREN
; Disable writes on write complete (EEIF set)
相關PDF資料 |
PDF描述 |
|---|---|
| T89C51CC01UA-RLTIM | IC 8051 MCU FLASH 32K 44VQFP |
| T89C51CC01CA-SLSIM | IC 8051 MCU FLASH 32K 44PLCC |
| T89C51CC01CA-RLTIM | IC 8051 MCU FLASH 32K 44VQFP |
| AT91M55800A-33CI | IC ARM MCU 33MHZ 176-BGA |
| 10FMN-BMTR-A-TB | CONN FMN HSNG 10POS SGL REV SMD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T89C51CC02 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash |
| T89C51CC02_03 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:CAN Microcontrollers |
| T89C51CC02_0305 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory |
| T89C51CC02_0312 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:CAN Microcontrollers |
| T89C51CC02_06 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash |
發(fā)布緊急采購，3分鐘左右您將得到回復。