- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3856 > T89C51CC01UA-SLSIM (Atmel)IC 8051 MCU FLASH 32K 44PLCC PDF資料下載
參數(shù)資料
| 型號： | T89C51CC01UA-SLSIM |
| 廠商： | Atmel |
| 文件頁數(shù)： | 119/123頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU FLASH 32K 44PLCC |
| 標準包裝： | 27 |
| 系列： | AT89C CAN |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | CAN，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 2K x 8 |
| RAM 容量： | 1.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 配用： | AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN |
| 其它名稱： | T89C51CC01UASLSIM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁當前第119頁第120頁第121頁第122頁第123頁
2010 Microchip Technology Inc.
DS41303G-page 95
PIC18F2XK20/4XK20
6.5
Writing to Flash Program Memory
The programming block size is 16, 32 or 64 bytes,
depending on the device (See Table 6-1). Word or byte
programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (See Table 6-1).
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 16, 32
or 64 times, depending on the device, for each pro-
gramming operation. All of the table write operations
will essentially be short writes because only the holding
registers are written. After all the holding registers have
been written, the programming operation of that block
of memory is started by configuring the EECON1 reg-
ister for a program memory write and performing the
long write sequence.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted during a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
Read 64 bytes into RAM.
2.
Update data values in RAM as necessary.
3.
Load Table Pointer register with address being
erased.
4.
Execute the block erase procedure.
5.
Load Table Pointer register with address of first
byte being written.
6.
Write the 16, 32 or 64 byte block into the holding
registers with auto-increment.
7.
Set the EECON1 register for the write operation:
set EEPGD bit to point to program memory;
clear the CFGS bit to access program memory;
set WREN to enable byte writes.
8.
Disable interrupts.
9.
Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6 to 13 for each block until all 64
bytes are written.
15. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in Example 6-3.
Note:
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all holding registers
before executing a long write operation.
TABLAT
TBLPTR = xxxxYY
(1)
TBLPTR = xxxx01
TBLPTR = xxxx00
Write Register
TBLPTR = xxxx02
Program Memory
Holding Register
8
Note 1: YY = x7, xF, or 1F for 8, 16 or 32 byte write blocks, respectively.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T89C51CC01UA-RLTIM | IC 8051 MCU FLASH 32K 44VQFP |
| T89C51CC01CA-SLSIM | IC 8051 MCU FLASH 32K 44PLCC |
| T89C51CC01CA-RLTIM | IC 8051 MCU FLASH 32K 44VQFP |
| AT91M55800A-33CI | IC ARM MCU 33MHZ 176-BGA |
| 10FMN-BMTR-A-TB | CONN FMN HSNG 10POS SGL REV SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T89C51CC02 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash |
| T89C51CC02_03 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:CAN Microcontrollers |
| T89C51CC02_0305 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory |
| T89C51CC02_0312 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:CAN Microcontrollers |
| T89C51CC02_06 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Enhanced 8-bit Microcontroller with CAN Controller and Flash |
發(fā)布緊急采購，3分鐘左右您將得到回復。