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| 型號： | STSAM9708 |
| 廠商： | Atmel Corp. |
| 英文描述： | Sound Synthesis |
| 中文描述： | 聲音合成 |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 373K |
| 代理商： | STSAM9708 |
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9
ATSAM9708
1772D–DRMSD–01/04
DSP RISC Signal
Processor
Each of the two DSP engines operates on a frame-timing basis with the frame subdi-
vided into 64 process slots. Each process is itself divided into 16 micro-instructions
known as “algorithms”. Up to 32 different DSP algorithms can be stored on-chip in each
DSP private Alg RAM memory, allowing the device to be programmed for a number of
audio signal generation/processing applications. Each DSP engine is capable of gener-
ating 64 simultaneous voices using algorithms such as wavetable synthesis with
interpolation, alternate loop and 24 dB resonant filtering for each voice, for a total
polyphony of 128 voices. Slots may be linked together (ML RAM) to allow implementa-
tion of more complex synthesis algorithms.
Each DSP also includes a 20 x 16 pipelined two’s complement multiplier, a 28-bit pipe-
lined adder and eight 24-bit final accumulators.
A typical application uses around 75% of the capacity of the DSP engines for synthesis,
thus providing a minimum of 96-voice wavetable polyphony. The remaining processing
power is used for typical function like reverberation, chorus, direct sound, surround
effect, equalizer, etc.
Frequently-accessed DSP parameter data are stored in 5 banks of on-chip RAM mem-
ory for each DSP. Sample data or delay lines, which are accessed relatively
infrequently, are stored in external ROM, SRAM, DRAM or SDRAM memory. The com-
bination of localized micro-program memory and localized parameter data allows micro-
instructions to execute in 20 ns (50 MIPS) on each DSP. Separate buses from each of
the on-chip parameter RAM memory banks allow highly parallel data movement to
increase the effectiveness of each micro-instruction. With this architecture, a single
micro-instruction can accomplish up to 6 simultaneous operations (add, multiply, load,
store, etc.), providing a total potential throughput of 600 million operations per second
(MOPS).
P16 Control
Processor and I/O
Functions
Each of the two P16 control processors is a general-purpose 16-bit CISC processor
core, that runs from external memory. A boot/macro ROM is included on-chip to acceler-
ate commonly executed routines and to allow the use of RAM only devices for the
external memory. Each P16 also includes 256 words of local RAM data memory.
Each P16 control processor writes to the parameter RAM blocks within its associated
DSP in order to control the synthesis process. In a typical application, the P16 control
processor parses and interprets incoming commands from the MIDI UART or from the
parallel 16-bit interface and then controls the DSP by writing into the parameter RAM
banks of its associated DSP core. Slowly-changing synthesis functions, such as LFOs,
are implemented in the P16 control processor by periodically updating the DSP parame-
ter RAM variables.
Each P16 control processor interfaces with other private peripheral devices, such as the
system control and status registers, the on-chip MIDI UART, the on-chip timers and the
ISA PC 16-bit interface through specialized “intelligent” peripheral I/O logic. This I/O
logic automates many of the system I/O transfers to minimize the amount of overhead
processing required from the P16.
The parallel interface is implemented using three address lines (A2, A1, A0), a chip
select signal, read and write strobes from the host and a 16-bit data bus (PC_D0 -
PC_D15).
This data bus cannot drive the PC bus directly. External buffers and an external decoder
(PAL) or plug and play IC are required to map the 16-bit I/O addresses and AEN from
the PC into the three address lines and chip select from the ATSAM9708.
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