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參數(shù)資料
| 型號： | STSAM9708 |
| 廠商： | Atmel Corp. |
| 英文描述： | Sound Synthesis |
| 中文描述： | 聲音合成 |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 373K |
| 代理商： | STSAM9708 |
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ATSAM9708
1772D–DRMSD–01/04
As RAS only counter refresh method is employed, several banks of DRAMs can be connected using simple external
CAS decoding. Linear address lines (WAx) can be used to select between DRAM banks. For example, a 1M x 32 SIMM
module may be connected as two 1M x 16 banks, with CAS0 and CAS1 selections issued from CAS and WA20.
During a whole DRAM cycle (from RAS low to CAS rising), WCS0 is asserted low.
The equivalence between multiplexed DRAM address lines (DRA0 to DRA11) and the corresponding linear addressing
(WA0 to WA23) is as follows:
To save DRAM power consumption, CAS and RAS are cycled only when necessary. Therefore, depending on firmware
loaded, total board power consumption may increase with synthesis processing traffic.
Detailed External ROM Timing
Figure 12.
ROM Read Cycle
DRA11
WA22
WA23
DRA10
WA20
WA21
DRA9
WA18
WA19
DRA8
WA8
WA17
DRA7
WA7
WA16
DRA6
WA6
WA15
DRA5
WA5
WA14
DRA4
WA4
WA13
DRA3
WA3
WA12
DRA2
WA2
WA11
DRA1
WA1
WA10
DRA0
WA0
WA9
RAS time
CAS time
Table 13.
External ROM Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
t
RC
Read cycle time
6 x t
CK
ns
t
AOE
Address valid to WOE low
t
CK
ns
t
POE
Output enable pulse width
5 x t
ck
ns
t
AD
Address access time
6 x t
CK
- 5
ns
t
OE
Output enable access time
5 x t
CK
- 5
ns
t
DF
Chip select or WOE high to input data
High Z
0
t
CK
- 5
ns
t
RC
t
AOE
t
POE
t
OE
t
AD
t
DF
WA[26:0]
WD[15:0]
WCS0
WOE
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