
27
ATSAM9708
1772D–DRMSD–01/04
Recommended Board
Layout
Like all HCMOS high-integration ICs, some rules of board layout should be followed for
reliable device operation:
GND, V
CC
, V
C3
Distribution,
Decouplings
All GND, V
CC
, V
C3
pins should be connected. GND and V
CC
planes are strongly recom-
mended below the ATSAM9708. The board GND and V
CC
distribution should be in grid
form. If 3.3V is not available, then V
C3
can be connected to V
CC
by two 1N4148 diodes in
series.
Recommended decoupling is 0.1 μF at each corner of the IC with an additional 10 μF
decoupling close to the crystal. V
C3
requires a single 0.1μF decoupling close to the IC.
Crystal, LFT
The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-
R and the ATSAM9708 should be short and shielded. The ground return from the com-
pensation capacitors and LFT filter should be the GND plane from ATSAM9708.
Buses
Parallel layout from PC_D[15:0] and DRA[11:0]/WD[15:0] should be avoided. The
PC_D[15:0] bus is an asynchronous high-transient current-type bus. Even on short dis-
tances, it can induce pulses on DRA[11:0]/WD[15:0] which can corrupt addresses
and/or data on these buses.
A ground plane should be implemented below the PC_D[15:0] bus, which connects both
to the PC-ISA connector and to the ATSAM9708 GND.
A ground plane should be implemented below the DRA[11:0]/WD[15:0] bus, which con-
nects both to the DRAM SIMM grounds and to the ATSAM9708.
Analog Section
A specific AGND ground plane should be provided, which connects to the GND ground
by a single trace. No digital signals should cross the AGND plane. Refer to the Codec
vendor recommended layout for correct implementation of the analog section.